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From: nork@cityfujisawa.ne.jp (Norikatsu Shigemura)
To: FreeBSD-tech-jp@jp.freebsd.org
In-Reply-To: Your message of "Sun, 28 Oct 2001 00:24:28 +0900".
	<011028002428.M0175783@pelsia.netmove.co.jp>
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Date: Sun, 28 Oct 2001 03:04:52 +0900
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Subject: [FreeBSD-tech-jp 3194] Re: agp driver for i840/i845/i850
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$B=EB<K!9n$G$9!#(B

2001/10/28 00:24 $B$K;d$O=q$-$^$7$?(B.
>> >> > # i845 $B$N%G!<%?%7!<%HC5$7$?$N$G$9$,8+Ev$?$i$J$$$G$9$M(B...
>> >> intel.com $B$N(B PDF $B$N(B Datasheet $B$J$i8+$D$+$j$^$7$?$,!"$=$l$8$cITB-$@$C$?$j(B
>> >> $B$7$^$9$+!)(B
>> 	$B$$$d!#$^$5$K$=$l$@$H;W$$$^$9!#(B
>> 	$B$d$C$QC5$7$,B-$j$J$+$C$?$+!D!#(Bdeveloper.intel.com $B8+$F$b(B
>> 	i840 $B$H$+(B i850 $B$O8+$($k$s$G$9$,!D!#(BURL $B65$($F$/$@$5$$!#(B m(_ _)m

	$B9M$($F8+$l$P(B, $B$"$k$3$H$OJ,$+$C$F$k$N$@$+$i8!:w$9$l$P0lH/$G$9$M(B(^^;$B!#(B
	$B$H$$$&$o$1$G8+IU$1$FMh$^$7$?!#(Bi850 $B$H$NHf3S$GBP1~$7$F$$$k$N$GBg>f(B
	$BIW$@$H$O;W$$$^$9$,(B, $B<B5!$bL5$$$7<+?.$O$"$j$^$;$s(B:-)$B!#(B

# $B$&$C:#$J$i(B Linux $B$h$j$b@h$K!D(B($BGz(B)...

--- sys/pci/agp_intel.c.orig	Wed Jul 19 18:48:04 2000
+++ sys/pci/agp_intel.c	Sun Oct 28 02:54:55 2001
@@ -74,6 +74,15 @@
 
  	case 0x71a18086:
  		return ("Intel 82443GX host to AGP bridge");
+
+	case 0x1a218086:
+ 		return ("Intel 82840 host to AGP bridge");
+
+	case 0x1a308086:
+ 		return ("Intel 82845 host to AGP bridge");
+
+	case 0x25308086:
+ 		return ("Intel 82850 host to AGP bridge");
 	};
 
 	if (pci_get_vendor(dev) == 0x8086)
@@ -102,6 +111,7 @@
 {
 	struct agp_intel_softc *sc = device_get_softc(dev);
 	struct agp_gatt *gatt;
+	u_int32_t type = pci_get_devid(dev);
 	int error;
 
 	error = agp_generic_attach(dev);
@@ -130,11 +140,42 @@
 	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
 	
 	/* Enable things, clear errors etc. */
-	pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
-	pci_write_config(dev, AGP_INTEL_NBXCFG,
-			 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-			  & ~(1 << 10)) | (1 << 9), 4);
-	pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
+	switch (type) {
+	case 0x1a218086: /* i840 */
+	case 0x25308086: /* i850 */
+		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
+		pci_write_config(dev, AGP_INTEL_MCHCFG,
+				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
+				  | (1 << 9)), 2);
+		break;
+
+	case 0x1a308086: /* i845 */
+		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
+		pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
+				 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 2)
+				  | (1 << 9)), 2);
+		break;
+
+	default: /* Intel Generic (maybe) */
+		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
+		pci_write_config(dev, AGP_INTEL_NBXCFG,
+				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
+				  & ~(1 << 10)) | (1 << 9), 4);
+	}
+
+	switch (type) {
+	case 0x1a218086: /* i840 */
+		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
+		break;
+
+	case 0x1a308086: /* i845 */
+	case 0x25308086: /* i850 */
+		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
+		break;
+
+	default: /* Intel Generic (maybe) */
+		pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
+	}
 
 	return 0;
 }
@@ -143,18 +184,39 @@
 agp_intel_detach(device_t dev)
 {
 	struct agp_intel_softc *sc = device_get_softc(dev);
+	u_int32_t type = pci_get_devid(dev);
 	int error;
 
 	error = agp_generic_detach(dev);
 	if (error)
 		return error;
 
-	printf("%s: set NBXCFG to %x\n", __FUNCTION__,
-			 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-			  & ~(1 << 9)));
-	pci_write_config(dev, AGP_INTEL_NBXCFG,
-			 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
-			  & ~(1 << 9)), 4);
+	switch (type) {
+	case 0x1a218086: /* i840 */
+	case 0x25308086: /* i850 */
+		printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
+				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
+				& ~(1 << 9)));
+		pci_write_config(dev, AGP_INTEL_MCHCFG,
+				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
+				& ~(1 << 9)), 2);
+
+	case 0x1a308086: /* i845 */
+		printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
+				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 2)
+				& ~(1 << 9)));
+		pci_write_config(dev, AGP_INTEL_MCHCFG,
+				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 2)
+				& ~(1 << 9)), 2);
+
+	default: /* Intel Generic (maybe) */
+		printf("%s: set NBXCFG to %x\n", __FUNCTION__,
+				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
+				  & ~(1 << 9)));
+		pci_write_config(dev, AGP_INTEL_NBXCFG,
+				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
+				  & ~(1 << 9)), 4);
+	}
 	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
 	AGP_SET_APERTURE(dev, sc->initial_aperture);
 	agp_free_gatt(sc->gatt);
--- sys/pci/agpreg.h.orig	Wed Jul 19 18:48:04 2000
+++ sys/pci/agpreg.h	Sun Oct 28 02:51:06 2001
@@ -57,6 +57,13 @@
 #define AGP_INTEL_ATTBASE	0xb8
 
 /*
+ * Config offsets for Intel i840/i845/i850 AGP chipsets.
+ */
+#define AGP_INTEL_MCHCFG	0x50
+#define AGP_INTEL_I845_MCHCFG	0x51
+#define AGP_INTEL_I8XX_ERRSTS	0xc8
+
+/*
  * Config offsets for VIA AGP chipsets.
  */
 #define AGP_VIA_GARTCTRL	0x80
