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From: ISHII <ishii_m@nifty.ne.jp>
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Date: Sun, 30 Jan 2005 23:23:43 +0900
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Subject: [FreeBSD-users-jp 82741] Re: on Dynabook SS S8
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ISHII$B$H?=$7$^$9!#(B

On Sun, 30 Jan 2005 01:18:15 +0900
TOGAWA Satoshi <toga@puyo.org> wrote:

> hint.elcr.0.disabled="1"
> hw.pci.enable_io_modes="0"
> 
> $B$G$-$l$P!$>e$N(B2$B9T(B($BFC$K>e$N9T(B)$B$,2?$r0UL#$7$F$$$k$+$r2r@b$7$F(B
> $B$$$?$@$1$k$H$"$j$,$?$$$G$9!$(B

/usr/src/sys/i386/isa/elcr.c $B$K$O!"(B

 * The ELCR is a register that controls the trigger mode and polarity of
 * EISA and ISA interrupts.  In FreeBSD 3.x and 4.x, the ELCR was only
 * consulted for determining the appropriate trigger mode of EISA
 * interrupts when using an APIC.  However, it seems that almost all
 * systems that include PCI also include an ELCR that manages the ISA
 * IRQs 0 through 15.  Thus, we check for the presence of an ELCR on
 * every machine by checking to see if the values found at bootup are
 * sane.  Note that the polarity of ISA and EISA IRQs are linked to the
 * trigger mode.  All edge triggered IRQs use active-hi polarity, and
 * all level triggered interrupts use active-lo polarity.
 *
 * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
 * controls IRQ 0, bit 1 controls IRQ 1, etc.  If the bit is zero, the
 * associated IRQ is edge triggered.  If the bit is one, the IRQ is
 * level triggered.

$B$H=q$+$l$F$$$^$9!#(B
$B1Q8l$OITF@0U$J$N$G$4<+J,$GLu$7$F$/$@$5$$!#0-$7$+$i$:!#(B

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    ISHII, Michiyasu
   ishii_m@nifty.com
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