
# Autogenerated by mlir-tblgen; don't manually edit.

from enum import IntEnum, auto, IntFlag
from ._ods_common import _cext as _ods_cext
from ..ir import register_attribute_builder
_ods_ir = _ods_cext.ir

class AddressSpace(IntEnum):
    """AMDGPU-specific address spaces"""

    FatRawBuffer = 0
    BufferRsrc = 1
    FatStructuredBuffer = 2

    def __str__(self):
        if self is AddressSpace.FatRawBuffer:
            return "fat_raw_buffer"
        if self is AddressSpace.BufferRsrc:
            return "buffer_rsrc"
        if self is AddressSpace.FatStructuredBuffer:
            return "fat_structured_buffer"
        raise ValueError("Unknown AddressSpace enum entry.")



class Scope(IntEnum):
    """AMDGPU-specific cache scopes. WGP - workgroup processor (CUs); SE - shader engine (GL2); DEV - device; SYS - system"""

    WGP = 0
    SE = 1
    DEV = 2
    SYS = 3

    def __str__(self):
        if self is Scope.WGP:
            return "WGP"
        if self is Scope.SE:
            return "SE"
        if self is Scope.DEV:
            return "DEV"
        if self is Scope.SYS:
            return "SYS"
        raise ValueError("Unknown Scope enum entry.")



class DPPPerm(IntEnum):
    """The possible permutations for a DPP operation"""

    quad_perm = 0
    row_shl = 1
    row_shr = 2
    row_ror = 3
    wave_shl = 4
    wave_shr = 5
    wave_ror = 6
    wave_rol = 7
    row_mirror = 8
    row_half_mirror = 9
    row_bcast_15 = 10
    row_bcast_31 = 11

    def __str__(self):
        if self is DPPPerm.quad_perm:
            return "quad_perm"
        if self is DPPPerm.row_shl:
            return "row_shl"
        if self is DPPPerm.row_shr:
            return "row_shr"
        if self is DPPPerm.row_ror:
            return "row_ror"
        if self is DPPPerm.wave_shl:
            return "wave_shl"
        if self is DPPPerm.wave_shr:
            return "wave_shr"
        if self is DPPPerm.wave_ror:
            return "wave_ror"
        if self is DPPPerm.wave_rol:
            return "wave_rol"
        if self is DPPPerm.row_mirror:
            return "row_mirror"
        if self is DPPPerm.row_half_mirror:
            return "row_half_mirror"
        if self is DPPPerm.row_bcast_15:
            return "row_bcast_15"
        if self is DPPPerm.row_bcast_31:
            return "row_bcast_31"
        raise ValueError("Unknown DPPPerm enum entry.")



class LoadTemporalHint(IntEnum):
    """AMDGPU-specific prefetch temporal hints for load instructions. RT - regular temporal for both near and far caches; NT - non-temporal for both near and far caches; HT - high-priority temporal for both near and far caches; LU - last-use; NT_RT - non-temporal for near cache(s) and regular for far caches; RT_NT - regular for near cache(s) and non-temporal for far caches; NT_HT - non-temporal for near cache(s) and high-priority temporal for far caches"""

    RT = 0
    NT = 1
    HT = 2
    LU = 3
    NT_RT = 4
    RT_NT = 5
    NT_HT = 6

    def __str__(self):
        if self is LoadTemporalHint.RT:
            return "RT"
        if self is LoadTemporalHint.NT:
            return "NT"
        if self is LoadTemporalHint.HT:
            return "HT"
        if self is LoadTemporalHint.LU:
            return "LU"
        if self is LoadTemporalHint.NT_RT:
            return "NT_RT"
        if self is LoadTemporalHint.RT_NT:
            return "RT_NT"
        if self is LoadTemporalHint.NT_HT:
            return "NT_HT"
        raise ValueError("Unknown LoadTemporalHint enum entry.")



class MFMAPermB(IntEnum):
    """The possible permutations of the lanes storing B available in an MFMA"""

    none = 0
    bcast_first_32 = 1
    bcast_second_32 = 2
    rotate_16_right = 3
    bcast_first_16 = 4
    bcast_second_16 = 5
    bcast_third_16 = 6
    bcast_fourth_16 = 7

    def __str__(self):
        if self is MFMAPermB.none:
            return "none"
        if self is MFMAPermB.bcast_first_32:
            return "bcast_first_32"
        if self is MFMAPermB.bcast_second_32:
            return "bcast_second_32"
        if self is MFMAPermB.rotate_16_right:
            return "rotate_16_right"
        if self is MFMAPermB.bcast_first_16:
            return "bcast_first_16"
        if self is MFMAPermB.bcast_second_16:
            return "bcast_second_16"
        if self is MFMAPermB.bcast_third_16:
            return "bcast_third_16"
        if self is MFMAPermB.bcast_fourth_16:
            return "bcast_fourth_16"
        raise ValueError("Unknown MFMAPermB enum entry.")



class sched_barrier_opt_enum(IntFlag):
    """The possible options for scheduling barriers"""

    none = 0
    non_mem_non_sideffect = 1
    valu = 2
    salu = 4
    mfma_wmma = 8
    all_vmem = 16
    vmem_read = 32
    vmem_write = 64
    all_ds = 128
    ds_read = 256
    ds_write = 512
    transcendental = 1024

    def __iter__(self):
        return iter([case for case in type(self) if (self & case) is case and self is not case])
    def __len__(self):
        return bin(self).count("1")

    def __str__(self):
        if len(self) > 1:
            return "|".join(map(str, self))
        if self is sched_barrier_opt_enum.none:
            return "none"
        if self is sched_barrier_opt_enum.non_mem_non_sideffect:
            return "non_mem_non_sideffect"
        if self is sched_barrier_opt_enum.valu:
            return "valu"
        if self is sched_barrier_opt_enum.salu:
            return "salu"
        if self is sched_barrier_opt_enum.mfma_wmma:
            return "mfma_wmma"
        if self is sched_barrier_opt_enum.all_vmem:
            return "all_vmem"
        if self is sched_barrier_opt_enum.vmem_read:
            return "vmem_read"
        if self is sched_barrier_opt_enum.vmem_write:
            return "vmem_write"
        if self is sched_barrier_opt_enum.all_ds:
            return "all_ds"
        if self is sched_barrier_opt_enum.ds_read:
            return "ds_read"
        if self is sched_barrier_opt_enum.ds_write:
            return "ds_write"
        if self is sched_barrier_opt_enum.transcendental:
            return "transcendental"
        raise ValueError("Unknown sched_barrier_opt_enum enum entry.")



@register_attribute_builder("amdgpu.AMDGPU_AddressSpaceAttr")
def _amdgpu_addressspaceattr(x, context):
    return _ods_ir.Attribute.parse(f'#amdgpu.address_space<{str(x)}>', context=context)

@register_attribute_builder("amdgpu.AMDGPU_CacheScopeAttr")
def _amdgpu_cachescopeattr(x, context):
    return _ods_ir.Attribute.parse(f'#amdgpu<cache_scope {str(x)}>', context=context)

@register_attribute_builder("amdgpu.AMDGPU_DPPPermAttr")
def _amdgpu_dpppermattr(x, context):
    return _ods_ir.Attribute.parse(f'#amdgpu<dpp_perm {str(x)}>', context=context)

@register_attribute_builder("amdgpu.AMDGPU_LoadTemporalHintAttr")
def _amdgpu_loadtemporalhintattr(x, context):
    return _ods_ir.Attribute.parse(f'#amdgpu<load_temporal_hint {str(x)}>', context=context)

@register_attribute_builder("amdgpu.AMDGPU_MFMAPermBAttr")
def _amdgpu_mfmapermbattr(x, context):
    return _ods_ir.Attribute.parse(f'#amdgpu<mfma_perm_b {str(x)}>', context=context)

@register_attribute_builder("amdgpu.AMDGPU_SchedBarrierOpOptAttr")
def _amdgpu_schedbarrieropoptattr(x, context):
    return _ods_ir.Attribute.parse(f'#amdgpu.sched_barrier_opt<{str(x)}>', context=context)

