
# Autogenerated by mlir-tblgen; don't manually edit.

from ._ods_common import _cext as _ods_cext
from ._ods_common import (
    equally_sized_accessor as _ods_equally_sized_accessor,
    get_default_loc_context as _ods_get_default_loc_context,
    get_op_results_or_values as _get_op_results_or_values,
    segmented_accessor as _ods_segmented_accessor,
)
_ods_ir = _ods_cext.ir
_ods_cext.globals.register_traceback_file_exclusion(__file__)

import builtins
from typing import Any as _Any, Sequence as _Sequence, Union as _Union, Optional as _Optional
import sys as _sys
if _sys.version_info >= (3, 12):
  from collections.abc import Buffer as _Buffer  # pytype: disable=not-supported-yet
else:
  try:
    from typing_extensions import Buffer as _Buffer
  except ImportError:
    _Buffer = _Any


@_ods_cext.register_dialect
class _Dialect(_ods_ir.Dialect):
  DIALECT_NAMESPACE = "x86"

@_ods_cext.register_operation(_Dialect)
class AVX10DotInt8Op(_ods_ir.OpView):
  r"""
  The `dot` op is an AVX10-Int8 specific op that can lower to the proper
  LLVMAVX10-INT8 operation `llvm.vpdpbssd.512`.
  
  Multiply groups of 4 adjacent pairs of signed 8-bit integers in `a` with
  corresponding signed 8-bit integers in `b`, producing 4 intermediate signed 16-bit
  results. Sum these 4 results with the corresponding 32-bit integer in `w`, and
  store the packed 32-bit results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx10.dot.i8 %w, %a, %b : vector<64xi8> -> vector<16xi32>
  ```
  """

  OPERATION_NAME = "x86.avx10.dot.i8"

  _ODS_REGIONS = (0, True)

  def __init__(self, w: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(w)
    operands.append(a)
    operands.append(b)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def w(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[2]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(AVX10DotInt8Op)
class AVX10DotInt8OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx10.dot.i8"

  @builtins.property
  def w(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[2]

def avx10_dot_i8(w: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return AVX10DotInt8Op(w=w, a=a, b=b, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class BcstToPackedF32Op(_ods_ir.OpView):
  r"""
  #### From the Intel Intrinsics Guide:
  
  Convert scalar BF16 or F16 (16-bit) floating-point element stored at memory locations
  starting at location `__A` to a single-precision (32-bit) floating-point,
  broadcast it to packed single-precision (32-bit) floating-point elements,
  and store the results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx.bcst_to_f32.packed %a : memref<1xbf16> -> vector<8xf32>
  %dst = x86.avx.bcst_to_f32.packed %a : memref<1xf16> -> vector<8xf32>
  ```
  """

  OPERATION_NAME = "x86.avx.bcst_to_f32.packed"

  _ODS_REGIONS = (0, True)

  def __init__(self, dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.MemRefType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    results.append(dst)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    return self.operation.operands[0]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(BcstToPackedF32Op)
class BcstToPackedF32OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx.bcst_to_f32.packed"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    return self.operands[0]

def avx_bcst_to_f32_packed(dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.MemRefType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return BcstToPackedF32Op(dst=dst, a=a, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class CvtPackedEvenIndexedToF32Op(_ods_ir.OpView):
  r"""
  #### From the Intel Intrinsics Guide:
  
  Convert packed BF16 or F16 (16-bit) floating-point even-indexed elements stored at
  memory locations starting at location `__A` to packed single-precision
  (32-bit) floating-point elements, and store the results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx.cvt.packed.even.indexed_to_f32 %a : memref<16xbf16> -> vector<8xf32>
  %dst = x86.avx.cvt.packed.even.indexed_to_f32 %a : memref<16xf16> -> vector<8xf32>
  ```
  """

  OPERATION_NAME = "x86.avx.cvt.packed.even.indexed_to_f32"

  _ODS_REGIONS = (0, True)

  def __init__(self, dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.MemRefType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    results.append(dst)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    return self.operation.operands[0]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(CvtPackedEvenIndexedToF32Op)
class CvtPackedEvenIndexedToF32OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx.cvt.packed.even.indexed_to_f32"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    return self.operands[0]

def avx_cvt_packed_even_indexed_to_f32(dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.MemRefType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return CvtPackedEvenIndexedToF32Op(dst=dst, a=a, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class CvtPackedF32ToBF16Op(_ods_ir.OpView):
  r"""
  The `convert_f32_to_bf16` op is an AVX512-BF16 specific op that can lower
  to the proper LLVMAVX512BF16 operation `llvm.cvtneps2bf16` depending on
  the width of MLIR vectors it is applied to.
  
  #### From the Intel Intrinsics Guide:
  
  Convert packed single-precision (32-bit) floating-point elements in `a` to
  packed BF16 (16-bit) floating-point elements, and store the results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx512.cvt.packed.f32_to_bf16 %a : vector<8xf32> -> vector<8xbf16>
  ```
  """

  OPERATION_NAME = "x86.avx512.cvt.packed.f32_to_bf16"

  _ODS_REGIONS = (0, True)

  def __init__(self, dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.VectorType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    results.append(dst)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(CvtPackedF32ToBF16Op)
class CvtPackedF32ToBF16OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx512.cvt.packed.f32_to_bf16"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

def avx512_cvt_packed_f32_to_bf16(dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.VectorType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return CvtPackedF32ToBF16Op(dst=dst, a=a, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class CvtPackedOddIndexedToF32Op(_ods_ir.OpView):
  r"""
  #### From the Intel Intrinsics Guide:
  
  Convert packed BF16 or F16 (16-bit) floating-point odd-indexed elements stored at
  memory locations starting at location `__A` to packed single-precision
  (32-bit) floating-point elements, and store the results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx.cvt.packed.odd.indexed_to_f32 %a : memref<16xbf16> -> vector<8xf32>
  %dst = x86.avx.cvt.packed.odd.indexed_to_f32 %a : memref<16xf16> -> vector<8xf32>
  ```
  """

  OPERATION_NAME = "x86.avx.cvt.packed.odd.indexed_to_f32"

  _ODS_REGIONS = (0, True)

  def __init__(self, dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.MemRefType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    results.append(dst)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    return self.operation.operands[0]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(CvtPackedOddIndexedToF32Op)
class CvtPackedOddIndexedToF32OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx.cvt.packed.odd.indexed_to_f32"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    return self.operands[0]

def avx_cvt_packed_odd_indexed_to_f32(dst: _ods_ir.Type, a: _ods_ir.Value[_ods_ir.MemRefType], *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return CvtPackedOddIndexedToF32Op(dst=dst, a=a, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class DotBF16Op(_ods_ir.OpView):
  r"""
  The `dot` op is an AVX512-BF16 specific op that can lower to the proper
  LLVMAVX512BF16 operation `llvm.dpbf16ps` depending on the width of MLIR
  vectors it is applied to.
  
  #### From the Intel Intrinsics Guide:
  
  Compute dot-product of BF16 (16-bit) floating-point pairs in `a` and `b`,
  accumulating the intermediate single-precision (32-bit) floating-point
  elements with elements in `src`, and store the results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx512.dot %src, %a, %b : vector<32xbf16> -> vector<16xf32>
  ```
  """

  OPERATION_NAME = "x86.avx512.dot"

  _ODS_REGIONS = (0, True)

  def __init__(self, src: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(src)
    operands.append(a)
    operands.append(b)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def src(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[2]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(DotBF16Op)
class DotBF16OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx512.dot"

  @builtins.property
  def src(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[2]

def avx512_dot(src: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return DotBF16Op(src=src, a=a, b=b, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class DotInt8Op(_ods_ir.OpView):
  r"""
  The `dot` op is an AVX2-Int8 specific op that can lower to the proper
  LLVMAVX2-INT8 operation `llvm.vpdpbssd` depending on the width of MLIR
  vectors it is applied to.
  
  #### From the Intel Intrinsics Guide:
  
  Multiply groups of 4 adjacent pairs of signed 8-bit integers in `a` with 
  corresponding signed 8-bit integers in `b`, producing 4 intermediate signed 16-bit 
  results. Sum these 4 results with the corresponding 32-bit integer in `w`, and 
  store the packed 32-bit results in `dst`.
  
  Example:
  ```mlir
  %dst = x86.avx.dot.i8 %w, %a, %b : vector<32xi8> -> vector<8xi32>
  ```
  """

  OPERATION_NAME = "x86.avx.dot.i8"

  _ODS_REGIONS = (0, True)

  def __init__(self, w: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(w)
    operands.append(a)
    operands.append(b)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def w(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[2]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(DotInt8Op)
class DotInt8OpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx.dot.i8"

  @builtins.property
  def w(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[2]

def avx_dot_i8(w: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return DotInt8Op(w=w, a=a, b=b, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class DotOp(_ods_ir.OpView):
  r"""
  Computes the 4-way dot products of the lower and higher parts of the source
  vectors and broadcasts the two results to the lower and higher elements of
  the destination vector, respectively. Adding one element of the lower part
  to one element of the higher part in the destination vector yields the full
  dot product of the two source vectors.
  
  Example:
  
  ```mlir
  %0 = x86.avx.intr.dot %a, %b : vector<8xf32>
  %1 = vector.extract %0[%i0] : f32 from vector<8xf32>
  %2 = vector.extract %0[%i4] : f32 from vector<8xf32>
  %d = arith.addf %1, %2 : f32
  ```
  """

  OPERATION_NAME = "x86.avx.intr.dot"

  _ODS_REGIONS = (0, True)

  def __init__(self, a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    operands.append(b)
    _ods_context = _ods_get_default_loc_context(loc)
    if results is None: results = [operands[0].type] * 1
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def res(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(DotOp)
class DotOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx.intr.dot"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

def avx_intr_dot(a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return DotOp(a=a, b=b, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class MaskCompressOp(_ods_ir.OpView):
  r"""
  The mask.compress op is an AVX512 specific op that can lower to the
  `llvm.mask.compress` instruction. Instead of `src`, a constant vector
  vector attribute `constant_src` may be specified. If neither `src` nor
  `constant_src` is specified, the remaining elements in the result vector are
  set to zero.
  
  #### From the Intel Intrinsics Guide:
  
  Contiguously store the active integer/floating-point elements in `a` (those
  with their respective bit set in writemask `k`) to `dst`, and pass through the
  remaining elements from `src`.
  """

  OPERATION_NAME = "x86.avx512.mask.compress"

  _ODS_REGIONS = (0, True)

  def __init__(self, k: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], *, src: _Optional[_ods_ir.Value[_ods_ir.VectorType]] = None, constant_src: _Optional[_Union[_Any, _ods_ir.Attribute]] = None, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(k)
    operands.append(a)
    if src is not None: operands.append(src)
    _ods_context = _ods_get_default_loc_context(loc)
    if constant_src is not None: attributes["constant_src"] = (constant_src if (
        isinstance(constant_src, _ods_ir.Attribute) or
        not _ods_ir.AttrBuilder.contains('ElementsAttr')) else
          _ods_ir.AttrBuilder.get('ElementsAttr')(constant_src, context=_ods_context))
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def k(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def src(self) -> _Optional[_ods_ir.Value[_ods_ir.VectorType]]:
    return None if len(self.operation.operands) < 3 else self.operation.operands[2]

  @builtins.property
  def constant_src(self) -> _Optional[_ods_ir.Attribute]:
    if "constant_src" not in self.operation.attributes:
      return None
    return self.operation.attributes["constant_src"]

  @constant_src.setter
  def constant_src(self, value: _Optional[_ods_ir.Attribute]):
    if value is not None:
      self.operation.attributes["constant_src"] = value
    elif "constant_src" in self.operation.attributes:
      del self.operation.attributes["constant_src"]

  @constant_src.deleter
  def constant_src(self):
    del self.operation.attributes["constant_src"]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(MaskCompressOp)
class MaskCompressOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx512.mask.compress"

  @builtins.property
  def k(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

  @builtins.property
  def src(self) -> _Optional[_ods_ir.Value[_ods_ir.VectorType]]:
    return None if len(self.operands) < 3 else self.operands[2]

  @builtins.property
  def constant_src(self) -> _Optional[_ods_ir.Attribute]:
    if "constant_src" not in self.attributes:
      return None
    return self.attributes["constant_src"]

def avx512_mask_compress(k: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], *, src: _Optional[_ods_ir.Value[_ods_ir.VectorType]] = None, constant_src: _Optional[_Union[_Any, _ods_ir.Attribute]] = None, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return MaskCompressOp(k=k, a=a, src=src, constant_src=constant_src, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class MaskRndScaleOp(_ods_ir.OpView):
  r"""
  The mask.rndscale op is an AVX512 specific op that can lower to the proper
  LLVMAVX512 operation: `llvm.mask.rndscale.ps.512` or
  `llvm.mask.rndscale.pd.512` instruction depending on the type of vectors it
  is applied to.
  
  #### From the Intel Intrinsics Guide:
  
  Round packed floating-point elements in `a` to the number of fraction bits
  specified by `imm`, and store the results in `dst` using writemask `k`
  (elements are copied from src when the corresponding mask bit is not set).
  """

  OPERATION_NAME = "x86.avx512.mask.rndscale"

  _ODS_REGIONS = (0, True)

  def __init__(self, src: _ods_ir.Value[_ods_ir.VectorType], k: _ods_ir.Value[_ods_ir.IntegerType], a: _ods_ir.Value[_ods_ir.VectorType], imm: _ods_ir.Value, rounding: _ods_ir.Value[_ods_ir.IntegerType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(src)
    operands.append(k)
    operands.append(a)
    operands.append(imm)
    operands.append(rounding)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def src(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def k(self) -> _ods_ir.Value[_ods_ir.IntegerType]:
    return self.operation.operands[1]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[2]

  @builtins.property
  def imm(self) -> _ods_ir.Value:
    return self.operation.operands[3]

  @builtins.property
  def rounding(self) -> _ods_ir.Value[_ods_ir.IntegerType]:
    return self.operation.operands[4]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(MaskRndScaleOp)
class MaskRndScaleOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx512.mask.rndscale"

  @builtins.property
  def src(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def k(self) -> _ods_ir.Value[_ods_ir.IntegerType]:
    return self.operands[1]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[2]

  @builtins.property
  def imm(self) -> _ods_ir.Value:
    return self.operands[3]

  @builtins.property
  def rounding(self) -> _ods_ir.Value[_ods_ir.IntegerType]:
    return self.operands[4]

def avx512_mask_rndscale(src: _ods_ir.Value[_ods_ir.VectorType], k: _ods_ir.Value[_ods_ir.IntegerType], a: _ods_ir.Value[_ods_ir.VectorType], imm: _ods_ir.Value, rounding: _ods_ir.Value[_ods_ir.IntegerType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return MaskRndScaleOp(src=src, k=k, a=a, imm=imm, rounding=rounding, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class MaskScaleFOp(_ods_ir.OpView):
  r"""
  The `mask.scalef` op is an AVX512 specific op that can lower to the proper
  LLVMAVX512 operation: `llvm.mask.scalef.ps.512` or
  `llvm.mask.scalef.pd.512` depending on the type of MLIR vectors it is
  applied to.
  
  #### From the Intel Intrinsics Guide:
  
  Scale the packed floating-point elements in `a` using values from `b`, and
  store the results in `dst` using writemask `k` (elements are copied from src
  when the corresponding mask bit is not set).
  """

  OPERATION_NAME = "x86.avx512.mask.scalef"

  _ODS_REGIONS = (0, True)

  def __init__(self, src: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], k: _ods_ir.Value, rounding: _ods_ir.Value[_ods_ir.IntegerType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(src)
    operands.append(a)
    operands.append(b)
    operands.append(k)
    operands.append(rounding)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def src(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[2]

  @builtins.property
  def k(self) -> _ods_ir.Value:
    return self.operation.operands[3]

  @builtins.property
  def rounding(self) -> _ods_ir.Value[_ods_ir.IntegerType]:
    return self.operation.operands[4]

  @builtins.property
  def dst(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(MaskScaleFOp)
class MaskScaleFOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx512.mask.scalef"

  @builtins.property
  def src(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[2]

  @builtins.property
  def k(self) -> _ods_ir.Value:
    return self.operands[3]

  @builtins.property
  def rounding(self) -> _ods_ir.Value[_ods_ir.IntegerType]:
    return self.operands[4]

def avx512_mask_scalef(src: _ods_ir.Value[_ods_ir.VectorType], a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], k: _ods_ir.Value, rounding: _ods_ir.Value[_ods_ir.IntegerType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return MaskScaleFOp(src=src, a=a, b=b, k=k, rounding=rounding, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class RsqrtOp(_ods_ir.OpView):
  OPERATION_NAME = "x86.avx.rsqrt"

  _ODS_REGIONS = (0, True)

  def __init__(self, a: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    _ods_context = _ods_get_default_loc_context(loc)
    if results is None: results = [operands[0].type] * 1
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def b(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(RsqrtOp)
class RsqrtOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx.rsqrt"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

def avx_rsqrt(a: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult[_ods_ir.VectorType]:
  return RsqrtOp(a=a, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class TileLoadOp(_ods_ir.OpView):
  r"""
  Loads a tile from memory defined by a `base` and `indices`, with the
  shape defined by the 2-dim vector type of the result.
  The tile's rows are populated by reading contiguous elements starting
  at the `base`. For each tile row, the `base` is incremented by `stride`
  number of elements.
  
  The tile is loaded using the following indexing scheme:
  
  ```
  for row in enumerate(tile_rows):
    mem_row = base[i0, i1, ..., iN + row * stride]
    for col in enumerate(tile_cols):
      tile[row, col] = mem_row[col]
  ```
  
  If the `stride` is not provided, then the `base` buffer must be at least
  2-dimensional, and the `stride` is automatically inferred and corresponds
  to the stride of the buffer's second innermost dimension.
  
  The operation is eventually lowered into the "tileloadd" instruction
  with the corresponding tile configuration.
  
  With the write memory effect, each `x86.amx.tile_load` operation serves as
  a compilation hint to use a separate tile register.
  
  Example:
  
  ```mlir
    // Tile load from a 2-D memref with implicit stride.
    %0 = x86.amx.tile_load %arg0[%c0, %c0] : memref<?x?xi8> into !x86.amx.tile<16x64xi8>
  
    // Tile load from a 1-D memref with explicit stride.
    %0 = x86.amx.tile_load %arg0[%c0], %stride : memref<?xi8> into !x86.amx.tile<16x64xi8>
  ```
  """

  OPERATION_NAME = "x86.amx.tile_load"

  _ODS_OPERAND_SEGMENTS = [1,-1,0,]

  _ODS_REGIONS = (0, True)

  def __init__(self, res: _ods_ir.Type, base: _ods_ir.Value[_ods_ir.MemRefType], indices: _Sequence[_ods_ir.Value[_ods_ir.IndexType]], *, stride: _Optional[_ods_ir.Value[_ods_ir.IndexType]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(base)
    operands.append(_get_op_results_or_values(indices))
    operands.append(stride)
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    results.append(res)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def base(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 0)
    return operand_range[0]

  @builtins.property
  def indices(self) -> _ods_ir.OpOperandList[_ods_ir.IndexType]:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 1)
    return operand_range

  @builtins.property
  def stride(self) -> _Optional[_ods_ir.Value[_ods_ir.IndexType]]:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 2)
    return operand_range[0] if len(operand_range) > 0 else None

  @builtins.property
  def res(self) -> _ods_ir.OpResult:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(TileLoadOp)
class TileLoadOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.amx.tile_load"

  @builtins.property
  def base(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 0)
    return operand_range[0]

  @builtins.property
  def indices(self) -> _ods_ir.OpOperandList[_ods_ir.IndexType]:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 1)
    return operand_range

  @builtins.property
  def stride(self) -> _Optional[_ods_ir.Value[_ods_ir.IndexType]]:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 2)
    return operand_range[0] if len(operand_range) > 0 else None

def amx_tile_load(res: _ods_ir.Type, base: _ods_ir.Value[_ods_ir.MemRefType], indices: _Sequence[_ods_ir.Value[_ods_ir.IndexType]], *, stride: _Optional[_ods_ir.Value[_ods_ir.IndexType]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult:
  return TileLoadOp(res=res, base=base, indices=indices, stride=stride, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class TileMulFOp(_ods_ir.OpView):
  r"""
  Multiplies a "m x k" tile with a "k x n" tile and accumulates the results
  into a "m x n" destination tile. Supports "f32 <- bf16 x bf16" (with
  pairs of "bf16") and "f32 <- f8E5M2/f8E4M3FN x f8E5M2/f8E4M3FN".
  
  The operation is eventually lowered into the "tdpbf16ps/tdpbf8ps/tdpbhf8ps/
  tdphbf8ps/tdphf8ps" instruction with the corresponding tile configuration.
  
  Example:
  
  ```mlir
    %0 = x86.amx.tile_mulf %a, %b, %c
      : !x86.amx.tile<16x32xbf16>, !x86.amx.tile<16x32xbf16>, !x86.amx.tile<16x16xf32>
  ```
  """

  OPERATION_NAME = "x86.amx.tile_mulf"

  _ODS_REGIONS = (0, True)

  def __init__(self, lhs: _ods_ir.Value, rhs: _ods_ir.Value, acc: _ods_ir.Value, *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(lhs)
    operands.append(rhs)
    operands.append(acc)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def lhs(self) -> _ods_ir.Value:
    return self.operation.operands[0]

  @builtins.property
  def rhs(self) -> _ods_ir.Value:
    return self.operation.operands[1]

  @builtins.property
  def acc(self) -> _ods_ir.Value:
    return self.operation.operands[2]

  @builtins.property
  def res(self) -> _ods_ir.OpResult:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(TileMulFOp)
class TileMulFOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.amx.tile_mulf"

  @builtins.property
  def lhs(self) -> _ods_ir.Value:
    return self.operands[0]

  @builtins.property
  def rhs(self) -> _ods_ir.Value:
    return self.operands[1]

  @builtins.property
  def acc(self) -> _ods_ir.Value:
    return self.operands[2]

def amx_tile_mulf(lhs: _ods_ir.Value, rhs: _ods_ir.Value, acc: _ods_ir.Value, *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult:
  return TileMulFOp(lhs=lhs, rhs=rhs, acc=acc, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class TileMulIOp(_ods_ir.OpView):
  r"""
  Multiplies a "m x k" tile with a "k x n" tile and accumulates the results
  into a "m x n" destination tile. Supports all "si32 <- s/ui8 x s/ui8"
  combinations (4 bytes packed into dwords in the columns of both the
  source operand tiles; the zero or sign extension is specified with
  the attributes and default to sign extended).
  
  The operation is eventually lowered into one of the "tdpbssd",
  "tdpbsud", "tdpbusd", or "tdpbuud" instructions with the corresponding
  tile configuration.
  
  Example:
  
  ```mlir
    %0 = x86.amx.tile_muli %a zext, %b zext, %c
      : !x86.amx.tile<16x64xi8>, !x86.amx.tile<16x64xi8>, !x86.amx.tile<16x16xi32>
  ```
  """

  OPERATION_NAME = "x86.amx.tile_muli"

  _ODS_REGIONS = (0, True)

  def __init__(self, lhs: _ods_ir.Value, rhs: _ods_ir.Value, acc: _ods_ir.Value, *, isZextLhs: _Optional[bool] = None, isZextRhs: _Optional[bool] = None, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(lhs)
    operands.append(rhs)
    operands.append(acc)
    _ods_context = _ods_get_default_loc_context(loc)
    if bool(isZextLhs): attributes["isZextLhs"] = _ods_ir.UnitAttr.get(
      _ods_get_default_loc_context(loc))
    if bool(isZextRhs): attributes["isZextRhs"] = _ods_ir.UnitAttr.get(
      _ods_get_default_loc_context(loc))
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def lhs(self) -> _ods_ir.Value:
    return self.operation.operands[0]

  @builtins.property
  def rhs(self) -> _ods_ir.Value:
    return self.operation.operands[1]

  @builtins.property
  def acc(self) -> _ods_ir.Value:
    return self.operation.operands[2]

  @builtins.property
  def isZextLhs(self) -> bool:
    return "isZextLhs" in self.operation.attributes

  @isZextLhs.setter
  def isZextLhs(self, value):
    if bool(value):
      self.operation.attributes["isZextLhs"] = _ods_ir.UnitAttr.get()
    elif "isZextLhs" in self.operation.attributes:
      del self.operation.attributes["isZextLhs"]

  @isZextLhs.deleter
  def isZextLhs(self):
    del self.operation.attributes["isZextLhs"]

  @builtins.property
  def isZextRhs(self) -> bool:
    return "isZextRhs" in self.operation.attributes

  @isZextRhs.setter
  def isZextRhs(self, value):
    if bool(value):
      self.operation.attributes["isZextRhs"] = _ods_ir.UnitAttr.get()
    elif "isZextRhs" in self.operation.attributes:
      del self.operation.attributes["isZextRhs"]

  @isZextRhs.deleter
  def isZextRhs(self):
    del self.operation.attributes["isZextRhs"]

  @builtins.property
  def res(self) -> _ods_ir.OpResult:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(TileMulIOp)
class TileMulIOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.amx.tile_muli"

  @builtins.property
  def lhs(self) -> _ods_ir.Value:
    return self.operands[0]

  @builtins.property
  def rhs(self) -> _ods_ir.Value:
    return self.operands[1]

  @builtins.property
  def acc(self) -> _ods_ir.Value:
    return self.operands[2]

  @builtins.property
  def isZextLhs(self) -> bool:
    return "isZextLhs" in self.attributes

  @builtins.property
  def isZextRhs(self) -> bool:
    return "isZextRhs" in self.attributes

def amx_tile_muli(lhs: _ods_ir.Value, rhs: _ods_ir.Value, acc: _ods_ir.Value, *, is_zext_lhs: _Optional[bool] = None, is_zext_rhs: _Optional[bool] = None, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult:
  return TileMulIOp(lhs=lhs, rhs=rhs, acc=acc, isZextLhs=is_zext_lhs, isZextRhs=is_zext_rhs, results=results, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class TileStoreOp(_ods_ir.OpView):
  r"""
  Stores a tile to memory defined by a `base` and `indices`, with the
  shape defined by the 2-dim vector type of the value.
  The tile's rows are written contiguously to the buffer starting at
  the `base`. For each tile row, the `base` is incremented by `stride`
  number of elements.
  
  The tile is stored using the following indexing scheme:
  
  ```
  for row in enumerate(tile_rows):
    mem_row = base[i0, i1, ..., iN + row * stride]
    for col in enumerate(tile_cols):
      mem_row[col] = tile[row, col]
  ```
  
  If the `stride` is not provided, then the `base` buffer must be at least
  2-dimensional, and the `stride` is automatically inferred and corresponds
  to the stride of the buffer's second innermost dimension.
  
  The operation is eventually lowered into the "tilestored" instruction
  with the corresponding tile configuration.
  
  Example:
  
  ```mlir
    // Tile store to a 2-D memref with implicit stride.
    x86.amx.tile_store %arg1[%c0, %c0], %0 : memref<?x?xi8>, !x86.amx.tile<16x64xi8>
  
    // Tile store to a 1-D memref with explicit stride.
    x86.amx.tile_store %arg1[%c0], %0, %stride : memref<?xi8>, !x86.amx.tile<16x64xi8>
  ```
  """

  OPERATION_NAME = "x86.amx.tile_store"

  _ODS_OPERAND_SEGMENTS = [1,-1,1,0,]

  _ODS_REGIONS = (0, True)

  def __init__(self, base: _ods_ir.Value[_ods_ir.MemRefType], indices: _Sequence[_ods_ir.Value[_ods_ir.IndexType]], val: _ods_ir.Value, *, stride: _Optional[_ods_ir.Value[_ods_ir.IndexType]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(base)
    operands.append(_get_op_results_or_values(indices))
    operands.append(val)
    operands.append(stride)
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def base(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 0)
    return operand_range[0]

  @builtins.property
  def indices(self) -> _ods_ir.OpOperandList[_ods_ir.IndexType]:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 1)
    return operand_range

  @builtins.property
  def val(self) -> _ods_ir.Value:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 2)
    return operand_range[0]

  @builtins.property
  def stride(self) -> _Optional[_ods_ir.Value[_ods_ir.IndexType]]:
    operand_range = _ods_segmented_accessor(
         self.operation.operands,
         self.operation.attributes["operandSegmentSizes"], 3)
    return operand_range[0] if len(operand_range) > 0 else None

@_ods_cext.register_op_adaptor(TileStoreOp)
class TileStoreOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.amx.tile_store"

  @builtins.property
  def base(self) -> _ods_ir.Value[_ods_ir.MemRefType]:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 0)
    return operand_range[0]

  @builtins.property
  def indices(self) -> _ods_ir.OpOperandList[_ods_ir.IndexType]:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 1)
    return operand_range

  @builtins.property
  def val(self) -> _ods_ir.Value:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 2)
    return operand_range[0]

  @builtins.property
  def stride(self) -> _Optional[_ods_ir.Value[_ods_ir.IndexType]]:
    operand_range = _ods_segmented_accessor(
         self.operands,
         self.attributes["operandSegmentSizes"], 3)
    return operand_range[0] if len(operand_range) > 0 else None

def amx_tile_store(base: _ods_ir.Value[_ods_ir.MemRefType], indices: _Sequence[_ods_ir.Value[_ods_ir.IndexType]], val: _ods_ir.Value, *, stride: _Optional[_ods_ir.Value[_ods_ir.IndexType]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> TileStoreOp:
  return TileStoreOp(base=base, indices=indices, val=val, stride=stride, loc=loc, ip=ip)

@_ods_cext.register_operation(_Dialect)
class TileZeroOp(_ods_ir.OpView):
  r"""
  Zeroes the destination tile, with the shape defined by the 2-dim
  vector type of the result.
  
  The operation is eventually lowered into the "tilezero" instruction
  with the corresponding tile configuration.
  
  With the write memory effect, each `x86.amx.tile_zero` operation serves as
  a compilation hint to use a separate tile register.
  
  Example:
  
  ```mlir
    %0 = x86.amx.tile_zero : !x86.amx.tile<16x16xbf16>
  ```
  """

  OPERATION_NAME = "x86.amx.tile_zero"

  _ODS_REGIONS = (0, True)

  def __init__(self, res: _ods_ir.Type, *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    _ods_context = _ods_get_default_loc_context(loc)
    results = []
    results.append(res)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def res(self) -> _ods_ir.OpResult:
    return self.operation.results[0]

@_ods_cext.register_op_adaptor(TileZeroOp)
class TileZeroOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.amx.tile_zero"

def amx_tile_zero(res: _ods_ir.Type, *, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResult:
  return TileZeroOp(res=res, loc=loc, ip=ip).result

@_ods_cext.register_operation(_Dialect)
class Vp2IntersectOp(_ods_ir.OpView):
  r"""
  The `vp2intersect` op is an AVX512 specific op that can lower to the proper
  LLVMAVX512 operation: `llvm.vp2intersect.d.512` or
  `llvm.vp2intersect.q.512` depending on the type of MLIR vectors it is
  applied to.
  
  #### From the Intel Intrinsics Guide:
  
  Compute intersection of packed integer vectors `a` and `b`, and store
  indication of match in the corresponding bit of two mask registers
  specified by `k1` and `k2`. A match in corresponding elements of `a` and
  `b` is indicated by a set bit in the corresponding bit of the mask
  registers.
  """

  OPERATION_NAME = "x86.avx512.vp2intersect"

  _ODS_REGIONS = (0, True)

  def __init__(self, a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None):
    operands = []
    attributes = {}
    regions = None
    operands.append(a)
    operands.append(b)
    _ods_context = _ods_get_default_loc_context(loc)
    _ods_successors = None
    super().__init__(self.OPERATION_NAME, self._ODS_REGIONS, self._ODS_OPERAND_SEGMENTS, self._ODS_RESULT_SEGMENTS, attributes=attributes, results=results, operands=operands, successors=_ods_successors, regions=regions, loc=loc, ip=ip)

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[0]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operation.operands[1]

  @builtins.property
  def k1(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[0]

  @builtins.property
  def k2(self) -> _ods_ir.OpResult[_ods_ir.VectorType]:
    return self.operation.results[1]

@_ods_cext.register_op_adaptor(Vp2IntersectOp)
class Vp2IntersectOpAdaptor(_ods_ir.OpAdaptor):
  OPERATION_NAME = "x86.avx512.vp2intersect"

  @builtins.property
  def a(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[0]

  @builtins.property
  def b(self) -> _ods_ir.Value[_ods_ir.VectorType]:
    return self.operands[1]

def avx512_vp2intersect(a: _ods_ir.Value[_ods_ir.VectorType], b: _ods_ir.Value[_ods_ir.VectorType], *, results: _Optional[_Sequence[_ods_ir.Type]] = None, loc: _Optional[_ods_ir.Location] = None, ip: _Optional[_ods_ir.InsertionPoint] = None) -> _ods_ir.OpResultList:
  return Vp2IntersectOp(a=a, b=b, results=results, loc=loc, ip=ip).results
