===========================
     APEX Boot Loader
     Freescale iMX3x
===========================


SDRAM Timing, tRC and tRFC
--------------------------

The CPU SDRAM controller allows setting of timing parameters on a bank
by bank basis via the ESDCFGx registers.  Datasheets for memory
(Micron) define their parameters with the same names as the MX31
datasheet, except for tRC and tRFC.  The MX31 timing value for tRC
should be the greater of these values in the SDRAM datasheet.

In the case of the Micron MT46H16M32LF 512Mib x32, the minimum tRFC is
shorter than the minimum tRC so the default timing of 10 clocks (75ns)
is adequate.  The Micron MT46H32M32LF 1Gib x32 has a tRC of 60ns (-6
part) and a tRFC of 110ns.  So, in this case the tRC must be much
longer.  We use 15 cycles to meet give 112ns for tRFC.


  