===========================
     APEX Boot Loader
Orion 5x (Feroceon 88F5182)
===========================


Pin Multiplexing
----------------

It looks like Gigabit Ethernet requires the pins necessary to run
UART1.


Default Memory Map
------------------

  Interface		Address Range		Target ID	Attribute
  -----------------------------------------------------------------------
  DDR SDRAM CS0		0x00000000 0x0fffffff	0x0		0x0e
  DDR SDRAM CS1		0x10000000 0x1fffffff	0x0		0x0d
  DDR SDRAM CS2		0x20000000 0x2fffffff	0x0		0x0b
  DDR SDRAM CS3		0x30000000 0x3fffffff	0x0		0x07
  PCI Express Memory	0x80000000 0x9fffffff	0x4		0x59
  PCI Memory		0xa0000000 0xbfffffff	0x3		0x59
  PCI Express I/O	0xc0000000 0xc000ffff	0x4		0x51
  PCI I/O		0xc8000000 0xc800ffff	0x3		0x51
  Security Accel. SRAM	0xc8010000 0xc801ffff	0x9		0x00
  Internal Addresses	0xd0000000 0xd00fffff
  Device CS0		0xe0000000 0xe7ffffff	0x1		0x1e
  Device CS1		0xe8000000 0xefffffff	0x1		0x1d
  Device CS2		0xf0000000 0xf7ffffff	0x1		0x1b
  Flash Boot CS		0xf8000000 0xffffffff	0x1		0x0f

The Linux kernel expects the map to look like this:

  Internal Addresses	0xf1000000 0xf10fffff

0x20000     1  enable
	  7:4  target
         15:8  attr
         31:16 size
0x20004  31:16 base
0x20008  31:16 remap

Window 0:      Enabled, Target 4, Attr 0x59, Size 0x7ff (128MiB),
       	       Base 0x90000000, Remap 0x40000000
Window 1:      Enabled, Target 3, Attr 0x59, Size 0x7ff (128MiB),
       	       Base 0x98000000, Remap 0x98000000
Window 2:      Enabled, Target 4, Attr 0x51, Size 0xf (1MiB),
       	       Base 0xf0000000
Window 3:      Enabled, Target 3, Attr 0x51, Size 0xf (1MiB),
       	       Base 0xf0100000
Window 4:      Enabled, Target 1, Attr 0x0f, Size 0x7 (512KiB),	    # NOR flash
       	       Base 0xfff80000
Window 5:      Enabled, Target 1, Attr 0x1e, Size 0x1f (2MiB),
       	       Base 0xfa000000
Window 6:      Enabled, Target 1, Attr 0x1d, Size 0x1ff (32MiB),
       	       Base 0xf8000000
Window 7:      Enabled, Target 1, Attr 0x1b, Size 0xf (1MiB),
       	       Base 0xfa800000
Internal Map:  Base 0xf1000000


Marvell>> md 0xf1020000
f1020000: 07ff5941 90000000 40000000 00000000    AY.........@....
f1020010: 07ff5931 98000000 98000000 00000000    1Y..............
f1020020: 000f5141 f0000000 00000000 00000000    AQ..............
f1020030: 000f5131 f0100000 00000000 00000000    1Q..............
f1020040: 00070f11 fff80000 00000000 00000000    ................
f1020050: 001f1e11 fa000000 00000000 00000000    ................
f1020060: 01ff1d11 f8000000 00000000 00000000    ................
f1020070: 000f1b11 fa800000 00000000 00000000    ................
f1020080: f1000000 00000000 00000000 00000000    ................
f1020090: 00000000 00000000 00000000 00000000    ................
f10200a0: 00000000 00000000 00000000 00000000    ................
f10200b0: 00000000 00000000 00000000 00000000    ................
f10200c0: 00000000 00000000 00000000 00000000    ................
f10200d0: 00000000 00000000 00000000 00000000    ................
f10200e0: 00000000 00000000 00000000 00000000    ................
f10200f0: 00000000 00000000 00000000 00000000    ................


Target	  	   	ID	Attr	Max Size
-----------------------------------------------
PCI Express Memory	4	0x59	512 MiB
PCI Memory  		3	0x59	512 MiB
PCI Express IO		4	0x51	64 KiB
PCI I/O	    		3	0x51	64 KiB
Security Accelerator	9	0x00	64 KiB (8KiB Implemented)
Internal Addresses			1 MiB
Device CS0		1	0x1e	128MiB
Device CS1		1	0x1d	128MiB
Device CS2		1	0x1b	128MiB
Flash Boot CS		1	0x0f	128MiB
-----------------------------------------------



Clocks
------

There are three clock domains, TCLK, SYSCLK, and CPUCLK.  TCLK is the
MBus clock which is used for peripherals.  It defaults to 166MHz.
SYSCLK is the DDR and AHB clock.  It defaults to 166MHz.  The CPUCLK
is the CPU core clock.  It defaults to 500MHz.

The clock values are determined by pull-ups/downs on CPU pins.  TCLK
is determined separately from the other clocks.

