require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_PCI_AMRREG_H_)) {
    eval 'sub _PCI_AMRREG_H_ () {1;}' unless defined(&_PCI_AMRREG_H_);
    if(defined(&AMR_CRASH_ME)) {
	eval 'sub AMR_MAX_CMDS () {255;}' unless defined(&AMR_MAX_CMDS);
    } else {
	eval 'sub AMR_MAX_CMDS () {120;}' unless defined(&AMR_MAX_CMDS);
    }
    eval 'sub AMR_MAXLD () {40;}' unless defined(&AMR_MAXLD);
    eval 'sub AMR_MAX_CMDS_PU () {63;}' unless defined(&AMR_MAX_CMDS_PU);
    eval 'sub AMR_MAX_SEGS () {26;}' unless defined(&AMR_MAX_SEGS);
    eval 'sub AMR_MAX_CHANNEL () {3;}' unless defined(&AMR_MAX_CHANNEL);
    eval 'sub AMR_MAX_TARGET () {15;}' unless defined(&AMR_MAX_TARGET);
    eval 'sub AMR_MAX_LUN () {7;}' unless defined(&AMR_MAX_LUN);
    eval 'sub AMR_MAX_CDB_LEN () {0xa;}' unless defined(&AMR_MAX_CDB_LEN);
    eval 'sub AMR_MAX_REQ_SENSE_LEN () {0x20;}' unless defined(&AMR_MAX_REQ_SENSE_LEN);
    eval 'sub AMR_SECTOR_SIZE () {512;}' unless defined(&AMR_SECTOR_SIZE);
    eval 'sub AMR_CMD_LREAD () {0x1;}' unless defined(&AMR_CMD_LREAD);
    eval 'sub AMR_CMD_LWRITE () {0x2;}' unless defined(&AMR_CMD_LWRITE);
    eval 'sub AMR_CMD_PASS () {0x3;}' unless defined(&AMR_CMD_PASS);
    eval 'sub AMR_CMD_EXT_ENQUIRY () {0x4;}' unless defined(&AMR_CMD_EXT_ENQUIRY);
    eval 'sub AMR_CMD_ENQUIRY () {0x5;}' unless defined(&AMR_CMD_ENQUIRY);
    eval 'sub AMR_CMD_FLUSH () {0xa;}' unless defined(&AMR_CMD_FLUSH);
    eval 'sub AMR_CMD_EXT_ENQUIRY2 () {0xc;}' unless defined(&AMR_CMD_EXT_ENQUIRY2);
    eval 'sub AMR_CMD_GET_MACHINEID () {0x36;}' unless defined(&AMR_CMD_GET_MACHINEID);
    eval 'sub AMR_CMD_GET_INITIATOR () {0x7d;}' unless defined(&AMR_CMD_GET_INITIATOR);
    eval 'sub AMR_CMD_CONFIG () {0xa1;}' unless defined(&AMR_CMD_CONFIG);
    eval 'sub AMR_CONFIG_PRODUCT_INFO () {0xe;}' unless defined(&AMR_CONFIG_PRODUCT_INFO);
    eval 'sub AMR_CONFIG_ENQ3 () {0xf;}' unless defined(&AMR_CONFIG_ENQ3);
    eval 'sub AMR_CONFIG_ENQ3_SOLICITED_NOTIFY () {0x1;}' unless defined(&AMR_CONFIG_ENQ3_SOLICITED_NOTIFY);
    eval 'sub AMR_CONFIG_ENQ3_SOLICITED_FULL () {0x2;}' unless defined(&AMR_CONFIG_ENQ3_SOLICITED_FULL);
    eval 'sub AMR_CONFIG_ENQ3_UNSOLICITED () {0x3;}' unless defined(&AMR_CONFIG_ENQ3_UNSOLICITED);
    eval 'sub AMR_STATUS_SUCCESS () {0x;}' unless defined(&AMR_STATUS_SUCCESS);
    eval 'sub AMR_STATUS_ABORTED () {0x2;}' unless defined(&AMR_STATUS_ABORTED);
    eval 'sub AMR_STATUS_FAILED () {0x80;}' unless defined(&AMR_STATUS_FAILED);
    eval 'sub AMR_DRV_CURSTATE {
        my($x) = @_;
	    eval q((($x) & 0xf));
    }' unless defined(&AMR_DRV_CURSTATE);
    eval 'sub AMR_DRV_PREVSTATE {
        my($x) = @_;
	    eval q(((($x) >> 4) & 0xf));
    }' unless defined(&AMR_DRV_PREVSTATE);
    eval 'sub AMR_DRV_OFFLINE () {0x;}' unless defined(&AMR_DRV_OFFLINE);
    eval 'sub AMR_DRV_DEGRADED () {0x1;}' unless defined(&AMR_DRV_DEGRADED);
    eval 'sub AMR_DRV_OPTIMAL () {0x2;}' unless defined(&AMR_DRV_OPTIMAL);
    eval 'sub AMR_DRV_ONLINE () {0x3;}' unless defined(&AMR_DRV_ONLINE);
    eval 'sub AMR_DRV_FAILED () {0x4;}' unless defined(&AMR_DRV_FAILED);
    eval 'sub AMR_DRV_REBUILD () {0x5;}' unless defined(&AMR_DRV_REBUILD);
    eval 'sub AMR_DRV_HOTSPARE () {0x6;}' unless defined(&AMR_DRV_HOTSPARE);
    eval 'sub AMR_DRV_RAID_MASK () {0xf;}' unless defined(&AMR_DRV_RAID_MASK);
    eval 'sub AMR_DRV_WRITEBACK () {0x10;}' unless defined(&AMR_DRV_WRITEBACK);
    eval 'sub AMR_DRV_READHEAD () {0x20;}' unless defined(&AMR_DRV_READHEAD);
    eval 'sub AMR_DRV_ADAPTIVE () {0x40;}' unless defined(&AMR_DRV_ADAPTIVE);
    eval 'sub AMR_BATT_MODULE_MISSING () {0x1;}' unless defined(&AMR_BATT_MODULE_MISSING);
    eval 'sub AMR_BATT_LOW_VOLTAGE () {0x2;}' unless defined(&AMR_BATT_LOW_VOLTAGE);
    eval 'sub AMR_BATT_TEMP_HIGH () {0x4;}' unless defined(&AMR_BATT_TEMP_HIGH);
    eval 'sub AMR_BATT_PACK_MISSING () {0x8;}' unless defined(&AMR_BATT_PACK_MISSING);
    eval 'sub AMR_BATT_CHARGE_MASK () {0x30;}' unless defined(&AMR_BATT_CHARGE_MASK);
    eval 'sub AMR_BATT_CHARGE_DONE () {0x;}' unless defined(&AMR_BATT_CHARGE_DONE);
    eval 'sub AMR_BATT_CHARGE_INPROG () {0x10;}' unless defined(&AMR_BATT_CHARGE_INPROG);
    eval 'sub AMR_BATT_CHARGE_FAIL () {0x20;}' unless defined(&AMR_BATT_CHARGE_FAIL);
    eval 'sub AMR_BATT_CYCLES_EXCEEDED () {0x40;}' unless defined(&AMR_BATT_CYCLES_EXCEEDED);
    eval 'sub AMR_8LD_MAXDRIVES () {8;}' unless defined(&AMR_8LD_MAXDRIVES);
    eval 'sub AMR_8LD_MAXCHAN () {5;}' unless defined(&AMR_8LD_MAXCHAN);
    eval 'sub AMR_8LD_MAXTARG () {15;}' unless defined(&AMR_8LD_MAXTARG);
    eval 'sub AMR_8LD_MAXPHYSDRIVES () {( &AMR_8LD_MAXCHAN *  &AMR_8LD_MAXTARG);}' unless defined(&AMR_8LD_MAXPHYSDRIVES);
    eval 'sub AMR_SIG_431 () {0xfffe0001;}' unless defined(&AMR_SIG_431);
    eval 'sub AMR_SIG_438 () {0xfffd0002;}' unless defined(&AMR_SIG_438);
    eval 'sub AMR_SIG_762 () {0xfffc0003;}' unless defined(&AMR_SIG_762);
    eval 'sub AMR_SIG_T5 () {0xfffb0004;}' unless defined(&AMR_SIG_T5);
    eval 'sub AMR_SIG_466 () {0xfffa0005;}' unless defined(&AMR_SIG_466);
    eval 'sub AMR_SIG_467 () {0xfff90006;}' unless defined(&AMR_SIG_467);
    eval 'sub AMR_SIG_T7 () {0xfff80007;}' unless defined(&AMR_SIG_T7);
    eval 'sub AMR_SIG_490 () {0xfff70008;}' unless defined(&AMR_SIG_490);
    eval 'sub AMR_40LD_MAXDRIVES () {40;}' unless defined(&AMR_40LD_MAXDRIVES);
    eval 'sub AMR_40LD_MAXCHAN () {16;}' unless defined(&AMR_40LD_MAXCHAN);
    eval 'sub AMR_40LD_MAXTARG () {16;}' unless defined(&AMR_40LD_MAXTARG);
    eval 'sub AMR_40LD_MAXPHYSDRIVES () {256;}' unless defined(&AMR_40LD_MAXPHYSDRIVES);
    eval 'sub AMR_PARAM_REBUILD_RATE () {0x1;}' unless defined(&AMR_PARAM_REBUILD_RATE);
    eval 'sub AMR_PARAM_FLUSH_INTERVAL () {0x2;}' unless defined(&AMR_PARAM_FLUSH_INTERVAL);
    eval 'sub AMR_PARAM_SENSE_ALERT () {0x3;}' unless defined(&AMR_PARAM_SENSE_ALERT);
    eval 'sub AMR_PARAM_DRIVE_INSERTED () {0x4;}' unless defined(&AMR_PARAM_DRIVE_INSERTED);
    eval 'sub AMR_PARAM_BATTERY_STATUS () {0x5;}' unless defined(&AMR_PARAM_BATTERY_STATUS);
    eval 'sub AMR_LDRVOP_CHECK () {0x1;}' unless defined(&AMR_LDRVOP_CHECK);
    eval 'sub AMR_LDRVOP_INIT () {0x2;}' unless defined(&AMR_LDRVOP_INIT);
    eval 'sub AMR_LDRVOP_REBUILD () {0x3;}' unless defined(&AMR_LDRVOP_REBUILD);
    eval 'sub AMR_LDRVOP_SUCCESS () {0x;}' unless defined(&AMR_LDRVOP_SUCCESS);
    eval 'sub AMR_LDRVOP_FAILED () {0x1;}' unless defined(&AMR_LDRVOP_FAILED);
    eval 'sub AMR_LDRVOP_ABORTED () {0x2;}' unless defined(&AMR_LDRVOP_ABORTED);
    eval 'sub AMR_LDRVOP_CORRECTED () {0x3;}' unless defined(&AMR_LDRVOP_CORRECTED);
    eval 'sub AMR_LDRVOP_STARTED () {0x4;}' unless defined(&AMR_LDRVOP_STARTED);
    eval 'sub AMR_FORMAT_START () {0x1;}' unless defined(&AMR_FORMAT_START);
    eval 'sub AMR_FORMAT_COMPLETE () {0x2;}' unless defined(&AMR_FORMAT_COMPLETE);
    eval 'sub AMR_QUARTZ_SIG_REG () {0xa0;}' unless defined(&AMR_QUARTZ_SIG_REG);
    eval 'sub AMR_QUARTZ_SIG0 () {0xcccc;}' unless defined(&AMR_QUARTZ_SIG0);
    eval 'sub AMR_QUARTZ_SIG1 () {0x3344;}' unless defined(&AMR_QUARTZ_SIG1);
    eval 'sub AMR_QREG_IDB () {0x20;}' unless defined(&AMR_QREG_IDB);
    eval 'sub AMR_QREG_ODB () {0x2c;}' unless defined(&AMR_QREG_ODB);
    eval 'sub AMR_QIDB_SUBMIT () {0x1;}' unless defined(&AMR_QIDB_SUBMIT);
    eval 'sub AMR_QIDB_ACK () {0x2;}' unless defined(&AMR_QIDB_ACK);
    eval 'sub AMR_QODB_READY () {0x10001234;}' unless defined(&AMR_QODB_READY);
    eval 'sub AMR_SREG_CMD () {0x10;}' unless defined(&AMR_SREG_CMD);
    eval 'sub AMR_SREG_MBOX_BUSY () {0x10;}' unless defined(&AMR_SREG_MBOX_BUSY);
    eval 'sub AMR_SREG_TOGL () {0x11;}' unless defined(&AMR_SREG_TOGL);
    eval 'sub AMR_SREG_MBOX () {0x14;}' unless defined(&AMR_SREG_MBOX);
    eval 'sub AMR_SREG_MBOX_ENABLE () {0x18;}' unless defined(&AMR_SREG_MBOX_ENABLE);
    eval 'sub AMR_SREG_INTR () {0x1a;}' unless defined(&AMR_SREG_INTR);
    eval 'sub AMR_SCMD_POST () {0x10;}' unless defined(&AMR_SCMD_POST);
    eval 'sub AMR_SCMD_ACKINTR () {0x8;}' unless defined(&AMR_SCMD_ACKINTR);
    eval 'sub AMR_STOGL_ENABLE () {0xc0;}' unless defined(&AMR_STOGL_ENABLE);
    eval 'sub AMR_SINTR_VALID () {0x40;}' unless defined(&AMR_SINTR_VALID);
    eval 'sub AMR_SMBOX_BUSY_FLAG () {0x10;}' unless defined(&AMR_SMBOX_BUSY_FLAG);
    eval 'sub AMR_SMBOX_ENABLE_ADDR () {0x;}' unless defined(&AMR_SMBOX_ENABLE_ADDR);
}
1;
