require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_IC_MLXREG_H_)) {
    eval 'sub _IC_MLXREG_H_ () {1;}' unless defined(&_IC_MLXREG_H_);
    eval 'sub MLX_SECTOR_SIZE () {512;}' unless defined(&MLX_SECTOR_SIZE);
    eval 'sub MLX_CMD_ENQUIRY_OLD () {0x5;}' unless defined(&MLX_CMD_ENQUIRY_OLD);
    eval 'sub MLX_CMD_ENQUIRY () {0x53;}' unless defined(&MLX_CMD_ENQUIRY);
    eval 'sub MLX_CMD_ENQUIRY2 () {0x1c;}' unless defined(&MLX_CMD_ENQUIRY2);
    eval 'sub MLX_CMD_ENQSYSDRIVE () {0x19;}' unless defined(&MLX_CMD_ENQSYSDRIVE);
    eval 'sub MLX_CMD_READSG () {0xb6;}' unless defined(&MLX_CMD_READSG);
    eval 'sub MLX_CMD_WRITESG () {0xb7;}' unless defined(&MLX_CMD_WRITESG);
    eval 'sub MLX_CMD_READSG_OLD () {0x82;}' unless defined(&MLX_CMD_READSG_OLD);
    eval 'sub MLX_CMD_WRITESG_OLD () {0x83;}' unless defined(&MLX_CMD_WRITESG_OLD);
    eval 'sub MLX_CMD_FLUSH () {0xa;}' unless defined(&MLX_CMD_FLUSH);
    eval 'sub MLX_CMD_LOGOP () {0x72;}' unless defined(&MLX_CMD_LOGOP);
    eval 'sub MLX_CMD_REBUILDASYNC () {0x16;}' unless defined(&MLX_CMD_REBUILDASYNC);
    eval 'sub MLX_CMD_CHECKASYNC () {0x1e;}' unless defined(&MLX_CMD_CHECKASYNC);
    eval 'sub MLX_CMD_REBUILDSTAT () {0xc;}' unless defined(&MLX_CMD_REBUILDSTAT);
    eval 'sub MLX_CMD_STOPCHANNEL () {0x13;}' unless defined(&MLX_CMD_STOPCHANNEL);
    eval 'sub MLX_CMD_STARTCHANNEL () {0x12;}' unless defined(&MLX_CMD_STARTCHANNEL);
    eval 'sub MLX_CMD_READ_CONFIG () {0x4e;}' unless defined(&MLX_CMD_READ_CONFIG);
    eval 'sub MLX_CMD_WRITE_CONFIG () {0x4f;}' unless defined(&MLX_CMD_WRITE_CONFIG);
    eval 'sub MLX_CMD_READ_DK_CONFIG () {0x4a;}' unless defined(&MLX_CMD_READ_DK_CONFIG);
    eval 'sub MLX_CMD_WRITE_DK_CONFIG () {0x4b;}' unless defined(&MLX_CMD_WRITE_DK_CONFIG);
    eval 'sub MLX_CMD_DIRECT_CDB () {0x4;}' unless defined(&MLX_CMD_DIRECT_CDB);
    eval 'sub MLX_CMD_DEVICE_STATE () {0x50;}' unless defined(&MLX_CMD_DEVICE_STATE);
    eval 'sub MLX_CMD_READ_CONFIG2 () {0x3d;}' unless defined(&MLX_CMD_READ_CONFIG2);
    eval 'sub MLX_CMD_WRITE_CONFIG2 () {0x3c;}' unless defined(&MLX_CMD_WRITE_CONFIG2);
    if(defined(&_KERNEL)) {
	eval 'sub MLX_STATUS_OK () {0x;}' unless defined(&MLX_STATUS_OK);
	eval 'sub MLX_STATUS_RDWROFFLINE () {0x2;}' unless defined(&MLX_STATUS_RDWROFFLINE);
	eval 'sub MLX_STATUS_WEDGED () {0xdeaf;}' unless defined(&MLX_STATUS_WEDGED);
	eval 'sub MLX_STATUS_LOST () {0xdead;}' unless defined(&MLX_STATUS_LOST);
	eval 'sub MLX_STATUS_BUSY () {0xbabe;}' unless defined(&MLX_STATUS_BUSY);
	eval 'sub MLX_V1REG_IE () {0x9;}' unless defined(&MLX_V1REG_IE);
	eval 'sub MLX_V1REG_IDB () {0xd;}' unless defined(&MLX_V1REG_IDB);
	eval 'sub MLX_V1REG_ODB_EN () {0xe;}' unless defined(&MLX_V1REG_ODB_EN);
	eval 'sub MLX_V1REG_ODB () {0xf;}' unless defined(&MLX_V1REG_ODB);
	eval 'sub MLX_V1REG_MAILBOX () {0x10;}' unless defined(&MLX_V1REG_MAILBOX);
	eval 'sub MLX_V1_IDB_FULL () {0x1;}' unless defined(&MLX_V1_IDB_FULL);
	eval 'sub MLX_V1_IDB_INIT_BUSY () {0x2;}' unless defined(&MLX_V1_IDB_INIT_BUSY);
	eval 'sub MLX_V1_IDB_SACK () {0x2;}' unless defined(&MLX_V1_IDB_SACK);
	eval 'sub MLX_V1_IDB_RESET () {0x10;}' unless defined(&MLX_V1_IDB_RESET);
	eval 'sub MLX_V1_ODB_SAVAIL () {0x1;}' unless defined(&MLX_V1_ODB_SAVAIL);
	eval 'sub MLX_V1_ODB_RESET () {0x2;}' unless defined(&MLX_V1_ODB_RESET);
	eval 'sub MLX_V1_FWERROR_PEND () {0x4;}' unless defined(&MLX_V1_FWERROR_PEND);
	eval 'sub MLX_V3REG_MAILBOX () {0x;}' unless defined(&MLX_V3REG_MAILBOX);
	eval 'sub MLX_V3REG_STATUS_IDENT () {0xd;}' unless defined(&MLX_V3REG_STATUS_IDENT);
	eval 'sub MLX_V3REG_STATUS () {0xe;}' unless defined(&MLX_V3REG_STATUS);
	eval 'sub MLX_V3REG_IDB () {0x40;}' unless defined(&MLX_V3REG_IDB);
	eval 'sub MLX_V3REG_ODB () {0x41;}' unless defined(&MLX_V3REG_ODB);
	eval 'sub MLX_V3REG_IE () {0x43;}' unless defined(&MLX_V3REG_IE);
	eval 'sub MLX_V3REG_FWERROR () {0x3f;}' unless defined(&MLX_V3REG_FWERROR);
	eval 'sub MLX_V3REG_FWERROR_PARAM1 () {0x;}' unless defined(&MLX_V3REG_FWERROR_PARAM1);
	eval 'sub MLX_V3REG_FWERROR_PARAM2 () {0x1;}' unless defined(&MLX_V3REG_FWERROR_PARAM2);
	eval 'sub MLX_V3_IDB_FULL () {0x1;}' unless defined(&MLX_V3_IDB_FULL);
	eval 'sub MLX_V3_IDB_INIT_BUSY () {0x2;}' unless defined(&MLX_V3_IDB_INIT_BUSY);
	eval 'sub MLX_V3_IDB_SACK () {0x2;}' unless defined(&MLX_V3_IDB_SACK);
	eval 'sub MLX_V3_IDB_RESET () {0x8;}' unless defined(&MLX_V3_IDB_RESET);
	eval 'sub MLX_V3_ODB_SAVAIL () {0x1;}' unless defined(&MLX_V3_ODB_SAVAIL);
	eval 'sub MLX_V3_FWERROR_PEND () {0x4;}' unless defined(&MLX_V3_FWERROR_PEND);
	eval 'sub MLX_V4REG_MAILBOX () {0x1000;}' unless defined(&MLX_V4REG_MAILBOX);
	eval 'sub MLX_V4REG_STATUS_IDENT () {0x1018;}' unless defined(&MLX_V4REG_STATUS_IDENT);
	eval 'sub MLX_V4REG_STATUS () {0x101a;}' unless defined(&MLX_V4REG_STATUS);
	eval 'sub MLX_V4REG_IDB () {0x20;}' unless defined(&MLX_V4REG_IDB);
	eval 'sub MLX_V4REG_ODB () {0x2c;}' unless defined(&MLX_V4REG_ODB);
	eval 'sub MLX_V4REG_IE () {0x34;}' unless defined(&MLX_V4REG_IE);
	eval 'sub MLX_V4REG_FWERROR () {0x103f;}' unless defined(&MLX_V4REG_FWERROR);
	eval 'sub MLX_V4REG_FWERROR_PARAM1 () {0x1000;}' unless defined(&MLX_V4REG_FWERROR_PARAM1);
	eval 'sub MLX_V4REG_FWERROR_PARAM2 () {0x1001;}' unless defined(&MLX_V4REG_FWERROR_PARAM2);
	eval 'sub MLX_V4_IDB_FULL () {0x1;}' unless defined(&MLX_V4_IDB_FULL);
	eval 'sub MLX_V4_IDB_INIT_BUSY () {0x2;}' unless defined(&MLX_V4_IDB_INIT_BUSY);
	eval 'sub MLX_V4_IDB_HWMBOX_CMD () {0x1;}' unless defined(&MLX_V4_IDB_HWMBOX_CMD);
	eval 'sub MLX_V4_IDB_SACK () {0x2;}' unless defined(&MLX_V4_IDB_SACK);
	eval 'sub MLX_V4_IDB_MEMMBOX_CMD () {0x10;}' unless defined(&MLX_V4_IDB_MEMMBOX_CMD);
	eval 'sub MLX_V4_ODB_HWSAVAIL () {0x1;}' unless defined(&MLX_V4_ODB_HWSAVAIL);
	eval 'sub MLX_V4_ODB_MEMSAVAIL () {0x2;}' unless defined(&MLX_V4_ODB_MEMSAVAIL);
	eval 'sub MLX_V4_ODB_HWMBOX_ACK () {0x1;}' unless defined(&MLX_V4_ODB_HWMBOX_ACK);
	eval 'sub MLX_V4_ODB_MEMMBOX_ACK () {0x2;}' unless defined(&MLX_V4_ODB_MEMMBOX_ACK);
	eval 'sub MLX_V4_IE_MASK () {0xfb;}' unless defined(&MLX_V4_IE_MASK);
	eval 'sub MLX_V4_IE_DISINT () {0x4;}' unless defined(&MLX_V4_IE_DISINT);
	eval 'sub MLX_V4_FWERROR_PEND () {0x4;}' unless defined(&MLX_V4_FWERROR_PEND);
	eval 'sub MLX_V5REG_MAILBOX () {0x50;}' unless defined(&MLX_V5REG_MAILBOX);
	eval 'sub MLX_V5REG_STATUS_IDENT () {0x5d;}' unless defined(&MLX_V5REG_STATUS_IDENT);
	eval 'sub MLX_V5REG_STATUS () {0x5e;}' unless defined(&MLX_V5REG_STATUS);
	eval 'sub MLX_V5REG_IDB () {0x60;}' unless defined(&MLX_V5REG_IDB);
	eval 'sub MLX_V5REG_ODB () {0x61;}' unless defined(&MLX_V5REG_ODB);
	eval 'sub MLX_V5REG_IE () {0x34;}' unless defined(&MLX_V5REG_IE);
	eval 'sub MLX_V5REG_FWERROR () {0x63;}' unless defined(&MLX_V5REG_FWERROR);
	eval 'sub MLX_V5REG_FWERROR_PARAM1 () {0x50;}' unless defined(&MLX_V5REG_FWERROR_PARAM1);
	eval 'sub MLX_V5REG_FWERROR_PARAM2 () {0x51;}' unless defined(&MLX_V5REG_FWERROR_PARAM2);
	eval 'sub MLX_V5_IDB_EMPTY () {0x1;}' unless defined(&MLX_V5_IDB_EMPTY);
	eval 'sub MLX_V5_IDB_INIT_DONE () {0x2;}' unless defined(&MLX_V5_IDB_INIT_DONE);
	eval 'sub MLX_V5_IDB_HWMBOX_CMD () {0x1;}' unless defined(&MLX_V5_IDB_HWMBOX_CMD);
	eval 'sub MLX_V5_IDB_SACK () {0x2;}' unless defined(&MLX_V5_IDB_SACK);
	eval 'sub MLX_V5_IDB_RESET () {0x8;}' unless defined(&MLX_V5_IDB_RESET);
	eval 'sub MLX_V5_IDB_MEMMBOX_CMD () {0x10;}' unless defined(&MLX_V5_IDB_MEMMBOX_CMD);
	eval 'sub MLX_V5_ODB_HWSAVAIL () {0x1;}' unless defined(&MLX_V5_ODB_HWSAVAIL);
	eval 'sub MLX_V5_ODB_MEMSAVAIL () {0x2;}' unless defined(&MLX_V5_ODB_MEMSAVAIL);
	eval 'sub MLX_V5_ODB_HWMBOX_ACK () {0x1;}' unless defined(&MLX_V5_ODB_HWMBOX_ACK);
	eval 'sub MLX_V5_ODB_MEMMBOX_ACK () {0x2;}' unless defined(&MLX_V5_ODB_MEMMBOX_ACK);
	eval 'sub MLX_V5_IE_DISINT () {0x4;}' unless defined(&MLX_V5_IE_DISINT);
	eval 'sub MLX_V5_FWERROR_PEND () {0x4;}' unless defined(&MLX_V5_FWERROR_PEND);
    }
    eval 'sub MLX_ENQ_SFLAG_DEFWRERR () {0x1;}' unless defined(&MLX_ENQ_SFLAG_DEFWRERR);
    eval 'sub MLX_ENQ_SFLAG_BATTLOW () {0x2;}' unless defined(&MLX_ENQ_SFLAG_BATTLOW);
    eval 'sub MLX_ENQ_MISC_BBU () {0x8;}' unless defined(&MLX_ENQ_MISC_BBU);
    eval 'sub MLX_LOGOP_GET () {0x;}' unless defined(&MLX_LOGOP_GET);
    eval 'sub MLX_LOGMSG_SENSE () {0x;}' unless defined(&MLX_LOGMSG_SENSE);
    eval 'sub MLX_CF2_ACTV_NEG () {0x2;}' unless defined(&MLX_CF2_ACTV_NEG);
    eval 'sub MLX_CF2_NORSTRTRY () {0x80;}' unless defined(&MLX_CF2_NORSTRTRY);
    eval 'sub MLX_CF2_STRGWRK () {0x100;}' unless defined(&MLX_CF2_STRGWRK);
    eval 'sub MLX_CF2_HPSUPP () {0x200;}' unless defined(&MLX_CF2_HPSUPP);
    eval 'sub MLX_CF2_NODISCN () {0x400;}' unless defined(&MLX_CF2_NODISCN);
    eval 'sub MLX_CF2_ARM () {0x2000;}' unless defined(&MLX_CF2_ARM);
    eval 'sub MLX_CF2_OFM () {0x8000;}' unless defined(&MLX_CF2_OFM);
    eval 'sub MLX_CF2_AEMI () {( &MLX_CF2_ARM |  &MLX_CF2_OFM);}' unless defined(&MLX_CF2_AEMI);
    eval 'sub MLX_CF2_READAH () {0x1;}' unless defined(&MLX_CF2_READAH);
    eval 'sub MLX_CF2_BIOSDLY () {0x2;}' unless defined(&MLX_CF2_BIOSDLY);
    eval 'sub MLX_CF2_REASS1S () {0x10;}' unless defined(&MLX_CF2_REASS1S);
    eval 'sub MLX_CF2_FUAENABL () {0x40;}' unless defined(&MLX_CF2_FUAENABL);
    eval 'sub MLX_CF2_R5ALLS () {0x80;}' unless defined(&MLX_CF2_R5ALLS);
    eval 'sub MLX_CF2_BIOS_DIS () {0x1;}' unless defined(&MLX_CF2_BIOS_DIS);
    eval 'sub MLX_CF2_CDROM_DIS () {0x2;}' unless defined(&MLX_CF2_CDROM_DIS);
    eval 'sub MLX_CF2_GEOM_255 () {0x20;}' unless defined(&MLX_CF2_GEOM_255);
    eval 'sub MLX_SYS_DRV_WRITEBACK () {(1<<7);}' unless defined(&MLX_SYS_DRV_WRITEBACK);
    eval 'sub MLX_SYS_DRV_RAID0 () {0;}' unless defined(&MLX_SYS_DRV_RAID0);
    eval 'sub MLX_SYS_DRV_RAID1 () {1;}' unless defined(&MLX_SYS_DRV_RAID1);
    eval 'sub MLX_SYS_DRV_RAID3 () {3;}' unless defined(&MLX_SYS_DRV_RAID3);
    eval 'sub MLX_SYS_DRV_RAID5 () {5;}' unless defined(&MLX_SYS_DRV_RAID5);
    eval 'sub MLX_SYS_DRV_RAID6 () {6;}' unless defined(&MLX_SYS_DRV_RAID6);
    eval 'sub MLX_SYS_DRV_JBOD () {7;}' unless defined(&MLX_SYS_DRV_JBOD);
    eval 'sub MLX_SYS_DRV_INITTED () {0x81;;}' unless defined(&MLX_SYS_DRV_INITTED);
    eval 'sub MLX_PHYS_DRV_PRESENT () {0x1;}' unless defined(&MLX_PHYS_DRV_PRESENT);
    eval 'sub MLX_PHYS_DRV_OTHER () {0x;}' unless defined(&MLX_PHYS_DRV_OTHER);
    eval 'sub MLX_PHYS_DRV_DISK () {0x1;}' unless defined(&MLX_PHYS_DRV_DISK);
    eval 'sub MLX_PHYS_DRV_SEQUENTIAL () {0x2;}' unless defined(&MLX_PHYS_DRV_SEQUENTIAL);
    eval 'sub MLX_PHYS_DRV_CDROM () {0x3;}' unless defined(&MLX_PHYS_DRV_CDROM);
    eval 'sub MLX_PHYS_DRV_FAST20 () {0x8;}' unless defined(&MLX_PHYS_DRV_FAST20);
    eval 'sub MLX_PHYS_DRV_SYNC () {0x10;}' unless defined(&MLX_PHYS_DRV_SYNC);
    eval 'sub MLX_PHYS_DRV_FAST () {0x20;}' unless defined(&MLX_PHYS_DRV_FAST);
    eval 'sub MLX_PHYS_DRV_WIDE () {0x40;}' unless defined(&MLX_PHYS_DRV_WIDE);
    eval 'sub MLX_PHYS_DRV_TAG () {0x80;}' unless defined(&MLX_PHYS_DRV_TAG);
    eval 'sub MLX_PHYS_DRV_DEAD () {0x;}' unless defined(&MLX_PHYS_DRV_DEAD);
    eval 'sub MLX_PHYS_DRV_WRONLY () {0x2;}' unless defined(&MLX_PHYS_DRV_WRONLY);
    eval 'sub MLX_PHYS_DRV_ONLINE () {0x3;}' unless defined(&MLX_PHYS_DRV_ONLINE);
    eval 'sub MLX_PHYS_DRV_STANDBY () {0x10;}' unless defined(&MLX_PHYS_DRV_STANDBY);
    eval 'sub MLX_DCDB_NO_DATA () {0x;}' unless defined(&MLX_DCDB_NO_DATA);
    eval 'sub MLX_DCDB_DATA_IN () {0x1;}' unless defined(&MLX_DCDB_DATA_IN);
    eval 'sub MLX_DCDB_DATA_OUT () {0x2;}' unless defined(&MLX_DCDB_DATA_OUT);
    eval 'sub MLX_DCDB_EARLY_STATUS () {0x4;}' unless defined(&MLX_DCDB_EARLY_STATUS);
    eval 'sub MLX_DCDB_TIMEOUT_10S () {0x10;}' unless defined(&MLX_DCDB_TIMEOUT_10S);
    eval 'sub MLX_DCDB_TIMEOUT_60S () {0x20;}' unless defined(&MLX_DCDB_TIMEOUT_60S);
    eval 'sub MLX_DCDB_TIMEOUT_20M () {0x30;}' unless defined(&MLX_DCDB_TIMEOUT_20M);
    eval 'sub MLX_DCDB_TIMEOUT_24H () {0x40;}' unless defined(&MLX_DCDB_TIMEOUT_24H);
    eval 'sub MLX_DCDB_NO_AUTO_SENSE () {0x40;}' unless defined(&MLX_DCDB_NO_AUTO_SENSE);
    eval 'sub MLX_DCDB_DISCONNECT () {0x80;}' unless defined(&MLX_DCDB_DISCONNECT);
}
1;
