require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_ARM_CPUCONF_H_)) {
    eval 'sub _ARM_CPUCONF_H_ () {1;}' unless defined(&_ARM_CPUCONF_H_);
    if(defined(&_KERNEL_OPT)) {
	require './arm/opt_cputypes.ph';
	require './arm/opt_cpuoptions.ph';
    }
    if(defined(&CPU_XSCALE_PXA250) || defined(&CPU_XSCALE_PXA270)) {
	eval 'sub __CPU_XSCALE_PXA2XX () {1;}' unless defined(&__CPU_XSCALE_PXA2XX);
    }
    if(defined(&CPU_XSCALE_PXA2X0)) {
	warn("option\ CPU_XSCALE_PXA2X0\ is\ obsolete\.\ Use\ CPU_XSCALE_PXA250\ and\/or\ CPU_XSCALE_PXA270\.");
    }
    if(0) {
	if(defined(&_KERNEL_OPT)) {
	    eval 'sub CPU_NTYPES () {(defined( &CPU_ARM6) + defined( &CPU_ARM7) + defined( &CPU_ARM7TDMI) + defined( &CPU_ARM8) + defined( &CPU_ARM9) + defined( &CPU_ARM9E) + defined( &CPU_ARM10) + defined( &CPU_ARM11) + defined( &CPU_ARM1136) + defined( &CPU_ARM1176) + defined( &CPU_ARM11MPCORE) + defined( &CPU_CORTEX) + defined( &CPU_SA110) + defined( &CPU_SA1100) + defined( &CPU_SA1110) + defined( &CPU_FA526) + defined( &CPU_IXP12X0) + defined( &CPU_XSCALE) + defined( &CPU_SHEEVA));}' unless defined(&CPU_NTYPES);
	} else {
	    eval 'sub CPU_NTYPES () {2;}' unless defined(&CPU_NTYPES);
	}
    }
    if(!defined(&_KERNEL_OPT)) {
	eval 'sub ARM_ARCH_2 () {1;}' unless defined(&ARM_ARCH_2);
    } else {
	eval 'sub ARM_ARCH_2 () {0;}' unless defined(&ARM_ARCH_2);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_ARM6) || defined(&CPU_ARM7))) {
	eval 'sub ARM_ARCH_3 () {1;}' unless defined(&ARM_ARCH_3);
    } else {
	eval 'sub ARM_ARCH_3 () {0;}' unless defined(&ARM_ARCH_3);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_ARM7TDMI) || defined(&CPU_ARM8) || defined(&CPU_ARM9) || defined(&CPU_SA110) || defined(&CPU_SA1100) || defined(&CPU_FA526) || defined(&CPU_SA1110) || defined(&CPU_IXP12X0))) {
	eval 'sub ARM_ARCH_4 () {1;}' unless defined(&ARM_ARCH_4);
    } else {
	eval 'sub ARM_ARCH_4 () {0;}' unless defined(&ARM_ARCH_4);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_ARM9E) || defined(&CPU_ARM10) || defined(&CPU_XSCALE) || defined(&CPU_SHEEVA))) {
	eval 'sub ARM_ARCH_5 () {1;}' unless defined(&ARM_ARCH_5);
    } else {
	eval 'sub ARM_ARCH_5 () {0;}' unless defined(&ARM_ARCH_5);
    }
    if(defined(&CPU_ARM11) || defined(&CPU_ARM11MPCORE)) {
	eval 'sub ARM_ARCH_6 () {1;}' unless defined(&ARM_ARCH_6);
    } else {
	eval 'sub ARM_ARCH_6 () {0;}' unless defined(&ARM_ARCH_6);
    }
    if(defined(&CPU_CORTEX) || defined(&CPU_PJ4B)) {
	eval 'sub ARM_ARCH_7 () {1;}' unless defined(&ARM_ARCH_7);
    } else {
	eval 'sub ARM_ARCH_7 () {0;}' unless defined(&ARM_ARCH_7);
    }
    eval 'sub ARM_NARCH () {( &ARM_ARCH_2 +  &ARM_ARCH_3 +  &ARM_ARCH_4 +  &ARM_ARCH_5 +  &ARM_ARCH_6 +  &ARM_ARCH_7);}' unless defined(&ARM_NARCH);
    if((defined(&ARM_NARCH) ? &ARM_NARCH : undef) == 0) {
	die("ARM_NARCH\ is\ 0");
    }
    if((defined(&ARM_ARCH_5) ? &ARM_ARCH_5 : undef) || (defined(&ARM_ARCH_6) ? &ARM_ARCH_6 : undef) || (defined(&ARM_ARCH_7) ? &ARM_ARCH_7 : undef)) {
	eval 'sub THUMB_CODE () {1;}' unless defined(&THUMB_CODE);
    }
    if(!defined(&_KERNEL_OPT)) {
	eval 'sub ARM_MMU_MEMC () {1;}' unless defined(&ARM_MMU_MEMC);
    } else {
	eval 'sub ARM_MMU_MEMC () {0;}' unless defined(&ARM_MMU_MEMC);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_ARM6) || defined(&CPU_ARM7) || defined(&CPU_ARM7TDMI) || defined(&CPU_ARM8) || defined(&CPU_ARM9) || defined(&CPU_ARM9E) || defined(&CPU_ARM10) || defined(&CPU_FA526)) || defined(&CPU_SHEEVA)) {
	eval 'sub ARM_MMU_GENERIC () {1;}' unless defined(&ARM_MMU_GENERIC);
    } else {
	eval 'sub ARM_MMU_GENERIC () {0;}' unless defined(&ARM_MMU_GENERIC);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_SA110) || defined(&CPU_SA1100) || defined(&CPU_SA1110) || defined(&CPU_IXP12X0))) {
	eval 'sub ARM_MMU_SA1 () {1;}' unless defined(&ARM_MMU_SA1);
    } else {
	eval 'sub ARM_MMU_SA1 () {0;}' unless defined(&ARM_MMU_SA1);
    }
    if(!defined(&_KERNEL_OPT) || defined(&CPU_XSCALE)) {
	eval 'sub ARM_MMU_XSCALE () {1;}' unless defined(&ARM_MMU_XSCALE);
    } else {
	eval 'sub ARM_MMU_XSCALE () {0;}' unless defined(&ARM_MMU_XSCALE);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_ARM11)  && defined(&ARM11_COMPAT_MMU))) {
	eval 'sub ARM_MMU_V6C () {1;}' unless defined(&ARM_MMU_V6C);
    } else {
	eval 'sub ARM_MMU_V6C () {0;}' unless defined(&ARM_MMU_V6C);
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_ARM11)  && !defined(&ARM11_COMPAT_MMU))) {
	eval 'sub ARM_MMU_V6N () {1;}' unless defined(&ARM_MMU_V6N);
    } else {
	eval 'sub ARM_MMU_V6N () {0;}' unless defined(&ARM_MMU_V6N);
    }
    eval 'sub ARM_MMU_V6 () {( &ARM_MMU_V6C +  &ARM_MMU_V6N);}' unless defined(&ARM_MMU_V6);
    if(!defined(&_KERNEL_OPT) || defined(&CPU_ARMV7)) {
	eval 'sub ARM_MMU_V7 () {1;}' unless defined(&ARM_MMU_V7);
    } else {
	eval 'sub ARM_MMU_V7 () {0;}' unless defined(&ARM_MMU_V7);
    }
    if(!defined(&_KERNEL_OPT) || defined(&CPU_ARMV8)) {
	eval 'sub ARM_MMU_V8 () {1;}' unless defined(&ARM_MMU_V8);
    } else {
	eval 'sub ARM_MMU_V8 () {0;}' unless defined(&ARM_MMU_V8);
    }
    if(!defined(&_LOCORE)) {
	eval 'sub ARM_MMU_EXTENDED () {(( &ARM_MMU_MEMC +  &ARM_MMU_GENERIC +  &ARM_MMU_SA1 +  &ARM_MMU_XSCALE +  &ARM_MMU_V6C) == 0 && ( &ARM_MMU_V6N +  &ARM_MMU_V7 +  &ARM_MMU_V8) > 0);}' unless defined(&ARM_MMU_EXTENDED);
	if((defined(&ARM_MMU_EXTENDED) ? &ARM_MMU_EXTENDED : undef) == 0) {
	    undef(&ARM_MMU_EXTENDED) if defined(&ARM_MMU_EXTENDED);
	}
    }
    eval 'sub ARM_NMMUS () {( &ARM_MMU_MEMC +  &ARM_MMU_GENERIC +  &ARM_MMU_SA1 +  &ARM_MMU_XSCALE +  &ARM_MMU_V6N +  &ARM_MMU_V6C +  &ARM_MMU_V7 +  &ARM_MMU_V8);}' unless defined(&ARM_NMMUS);
    if((defined(&ARM_NMMUS) ? &ARM_NMMUS : undef) == 0) {
	die("ARM_NMMUS\ is\ 0");
    }
    if(!defined(&_KERNEL_OPT) || (defined(&CPU_XSCALE_80200) || defined(&CPU_XSCALE_80321))) {
	eval 'sub ARM_XSCALE_PMU () {1;}' unless defined(&ARM_XSCALE_PMU);
    } else {
	eval 'sub ARM_XSCALE_PMU () {0;}' unless defined(&ARM_XSCALE_PMU);
    }
}
1;
