require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_DEV_ATA_ATAREG_H_)) {
    eval 'sub _DEV_ATA_ATAREG_H_ () {1;}' unless defined(&_DEV_ATA_ATAREG_H_);
    eval 'sub WDCS_BSY () {0x80;}' unless defined(&WDCS_BSY);
    eval 'sub WDCS_DRDY () {0x40;}' unless defined(&WDCS_DRDY);
    eval 'sub WDCS_DWF () {0x20;}' unless defined(&WDCS_DWF);
    eval 'sub WDCS_DSC () {0x10;}' unless defined(&WDCS_DSC);
    eval 'sub WDCS_DRQ () {0x8;}' unless defined(&WDCS_DRQ);
    eval 'sub WDCS_CORR () {0x4;}' unless defined(&WDCS_CORR);
    eval 'sub WDCS_IDX () {0x2;}' unless defined(&WDCS_IDX);
    eval 'sub WDCS_ERR () {0x1;}' unless defined(&WDCS_ERR);
    eval 'sub WDCS_BITS () {"\\020\\010bsy\\007drdy\\006dwf\\005dsc\\004drq\\003corr\\002idx\\001err";}' unless defined(&WDCS_BITS);
    eval 'sub WDCE_BBK () {0x80;}' unless defined(&WDCE_BBK);
    eval 'sub WDCE_CRC () {0x80;}' unless defined(&WDCE_CRC);
    eval 'sub WDCE_UNC () {0x40;}' unless defined(&WDCE_UNC);
    eval 'sub WDCE_MC () {0x20;}' unless defined(&WDCE_MC);
    eval 'sub WDCE_IDNF () {0x10;}' unless defined(&WDCE_IDNF);
    eval 'sub WDCE_MCR () {0x8;}' unless defined(&WDCE_MCR);
    eval 'sub WDCE_ABRT () {0x4;}' unless defined(&WDCE_ABRT);
    eval 'sub WDCE_TK0NF () {0x2;}' unless defined(&WDCE_TK0NF);
    eval 'sub WDCE_AMNF () {0x1;}' unless defined(&WDCE_AMNF);
    eval 'sub WDCC_NOP () {0x;}' unless defined(&WDCC_NOP);
    eval 'sub ATA_DATA_SET_MANAGEMENT () {0x6;}' unless defined(&ATA_DATA_SET_MANAGEMENT);
    eval 'sub WDCC_RECAL () {0x10;}' unless defined(&WDCC_RECAL);
    eval 'sub WDCC_READ () {0x20;}' unless defined(&WDCC_READ);
    eval 'sub WDCC_READ_LOG_EXT () {0x2f;}' unless defined(&WDCC_READ_LOG_EXT);
    eval 'sub WDCC_LOG_PAGE_NCQ () {0x10;}' unless defined(&WDCC_LOG_PAGE_NCQ);
    eval 'sub WDCC_LOG_NQ () { &__BIT(7);}' unless defined(&WDCC_LOG_NQ);
    eval 'sub WDCC_WRITE () {0x30;}' unless defined(&WDCC_WRITE);
    eval 'sub WDCC__LONG () {0x2;}' unless defined(&WDCC__LONG);
    eval 'sub WDCC__NORETRY () {0x1;}' unless defined(&WDCC__NORETRY);
    eval 'sub WDCC_READ_LOG_DMA_EXT () {0x47;}' unless defined(&WDCC_READ_LOG_DMA_EXT);
    eval 'sub WDCC_FORMAT () {0x50;}' unless defined(&WDCC_FORMAT);
    eval 'sub WDCC_DIAGNOSE () {0x90;}' unless defined(&WDCC_DIAGNOSE);
    eval 'sub WDCC_IDP () {0x91;}' unless defined(&WDCC_IDP);
    eval 'sub WDCC_SMART () {0xb0;}' unless defined(&WDCC_SMART);
    eval 'sub WDCC_READMULTI () {0xc4;}' unless defined(&WDCC_READMULTI);
    eval 'sub WDCC_WRITEMULTI () {0xc5;}' unless defined(&WDCC_WRITEMULTI);
    eval 'sub WDCC_SETMULTI () {0xc6;}' unless defined(&WDCC_SETMULTI);
    eval 'sub WDCC_READDMA () {0xc8;}' unless defined(&WDCC_READDMA);
    eval 'sub WDCC_WRITEDMA () {0xca;}' unless defined(&WDCC_WRITEDMA);
    eval 'sub WDCC_ACKMC () {0xdb;}' unless defined(&WDCC_ACKMC);
    eval 'sub WDCC_LOCK () {0xde;}' unless defined(&WDCC_LOCK);
    eval 'sub WDCC_UNLOCK () {0xdf;}' unless defined(&WDCC_UNLOCK);
    eval 'sub WDCC_FLUSHCACHE () {0xe7;}' unless defined(&WDCC_FLUSHCACHE);
    eval 'sub WDCC_FLUSHCACHE_EXT () {0xea;}' unless defined(&WDCC_FLUSHCACHE_EXT);
    eval 'sub WDCC_IDENTIFY () {0xec;}' unless defined(&WDCC_IDENTIFY);
    eval 'sub SET_FEATURES () {0xef;}' unless defined(&SET_FEATURES);
    eval 'sub WDCC_IDLE () {0xe3;}' unless defined(&WDCC_IDLE);
    eval 'sub WDCC_IDLE_IMMED () {0xe1;}' unless defined(&WDCC_IDLE_IMMED);
    eval 'sub WDCC_SLEEP () {0xe6;}' unless defined(&WDCC_SLEEP);
    eval 'sub WDCC_STANDBY () {0xe2;}' unless defined(&WDCC_STANDBY);
    eval 'sub WDCC_STANDBY_IMMED () {0xe0;}' unless defined(&WDCC_STANDBY_IMMED);
    eval 'sub WDCC_CHECK_PWR () {0xe5;}' unless defined(&WDCC_CHECK_PWR);
    eval 'sub WDCC_SECURITY_SET_PASSWORD () {0xf1;}' unless defined(&WDCC_SECURITY_SET_PASSWORD);
    eval 'sub WDCC_SECURITY_UNLOCK () {0xf2;}' unless defined(&WDCC_SECURITY_UNLOCK);
    eval 'sub WDCC_SECURITY_ERASE_PREPARE () {0xf3;}' unless defined(&WDCC_SECURITY_ERASE_PREPARE);
    eval 'sub WDCC_SECURITY_ERASE_UNIT () {0xf4;}' unless defined(&WDCC_SECURITY_ERASE_UNIT);
    eval 'sub WDCC_SECURITY_FREEZE () {0xf5;}' unless defined(&WDCC_SECURITY_FREEZE);
    eval 'sub WDCC_SECURITY_DISABLE_PASSWORD () {0xf6;}' unless defined(&WDCC_SECURITY_DISABLE_PASSWORD);
    eval 'sub WDCC_READ_EXT () {0x24;}' unless defined(&WDCC_READ_EXT);
    eval 'sub WDCC_WRITE_EXT () {0x34;}' unless defined(&WDCC_WRITE_EXT);
    eval 'sub WDCC_READMULTI_EXT () {0x29;}' unless defined(&WDCC_READMULTI_EXT);
    eval 'sub WDCC_WRITEMULTI_EXT () {0x39;}' unless defined(&WDCC_WRITEMULTI_EXT);
    eval 'sub WDCC_READDMA_EXT () {0x25;}' unless defined(&WDCC_READDMA_EXT);
    eval 'sub WDCC_WRITEDMA_EXT () {0x35;}' unless defined(&WDCC_WRITEDMA_EXT);
    eval 'sub WDCC_WRITEDMA_FUA_EXT () {0x3d;}' unless defined(&WDCC_WRITEDMA_FUA_EXT);
    if(defined(&_KERNEL) || defined(&_STANDALONE)) {
	require 'dev/ata/ataconf.ph';
	if((defined(&NATA_DMA) ? &NATA_DMA : undef)) {
	}
    }
    eval 'sub WDCC_READ_FPDMA_QUEUED () {0x60;}' unless defined(&WDCC_READ_FPDMA_QUEUED);
    eval 'sub WDCC_WRITE_FPDMA_QUEUED () {0x61;}' unless defined(&WDCC_WRITE_FPDMA_QUEUED);
    eval 'sub WDSF_8BIT_PIO_EN () {0x1;}' unless defined(&WDSF_8BIT_PIO_EN);
    eval 'sub WDSF_WRITE_CACHE_EN () {0x2;}' unless defined(&WDSF_WRITE_CACHE_EN);
    eval 'sub WDSF_SET_MODE () {0x3;}' unless defined(&WDSF_SET_MODE);
    eval 'sub WDSF_REASSIGN_EN () {0x4;}' unless defined(&WDSF_REASSIGN_EN);
    eval 'sub WDSF_APM_EN () {0x5;}' unless defined(&WDSF_APM_EN);
    eval 'sub WDSF_PUIS_EN () {0x6;}' unless defined(&WDSF_PUIS_EN);
    eval 'sub WDSF_PUIS_SPIN_UP () {0x7;}' unless defined(&WDSF_PUIS_SPIN_UP);
    eval 'sub WDSF_SATA_EN () {0x10;}' unless defined(&WDSF_SATA_EN);
    eval 'sub WDSF_RETRY_DS () {0x33;}' unless defined(&WDSF_RETRY_DS);
    eval 'sub WDSF_AAM_EN () {0x42;}' unless defined(&WDSF_AAM_EN);
    eval 'sub WDSF_SET_CACHE_SGMT () {0x54;}' unless defined(&WDSF_SET_CACHE_SGMT);
    eval 'sub WDSF_READAHEAD_DS () {0x55;}' unless defined(&WDSF_READAHEAD_DS);
    eval 'sub WDSF_POD_DS () {0x66;}' unless defined(&WDSF_POD_DS);
    eval 'sub WDSF_ECC_DS () {0x77;}' unless defined(&WDSF_ECC_DS);
    eval 'sub WDSF_WRITE_CACHE_DS () {0x82;}' unless defined(&WDSF_WRITE_CACHE_DS);
    eval 'sub WDSF_REASSIGN_DS () {0x84;}' unless defined(&WDSF_REASSIGN_DS);
    eval 'sub WDSF_APM_DS () {0x85;}' unless defined(&WDSF_APM_DS);
    eval 'sub WDSF_PUIS_DS () {0x86;}' unless defined(&WDSF_PUIS_DS);
    eval 'sub WDSF_ECC_EN () {0x88;}' unless defined(&WDSF_ECC_EN);
    eval 'sub WDSF_SATA_DS () {0x90;}' unless defined(&WDSF_SATA_DS);
    eval 'sub WDSF_RETRY_EN () {0x99;}' unless defined(&WDSF_RETRY_EN);
    eval 'sub WDSF_SET_CURRENT () {0x9a;}' unless defined(&WDSF_SET_CURRENT);
    eval 'sub WDSF_READAHEAD_EN () {0xaa;}' unless defined(&WDSF_READAHEAD_EN);
    eval 'sub WDSF_PREFETCH_SET () {0xab;}' unless defined(&WDSF_PREFETCH_SET);
    eval 'sub WDSF_AAM_DS () {0xc2;}' unless defined(&WDSF_AAM_DS);
    eval 'sub WDSF_POD_EN () {0xcc;}' unless defined(&WDSF_POD_EN);
    eval 'sub WDSF_SATA_NONZERO_OFFSETS () {0x1;}' unless defined(&WDSF_SATA_NONZERO_OFFSETS);
    eval 'sub WDSF_SATA_DMA_SETUP_AUTO () {0x2;}' unless defined(&WDSF_SATA_DMA_SETUP_AUTO);
    eval 'sub WDSF_SATA_DRIVE_PWR_MGMT () {0x3;}' unless defined(&WDSF_SATA_DRIVE_PWR_MGMT);
    eval 'sub WDSF_SATA_IN_ORDER_DATA () {0x4;}' unless defined(&WDSF_SATA_IN_ORDER_DATA);
    eval 'sub WDSF_SATA_ASYNC_NOTIFY () {0x5;}' unless defined(&WDSF_SATA_ASYNC_NOTIFY);
    eval 'sub WDSF_SATA_SW_STTNGS_PRS () {0x6;}' unless defined(&WDSF_SATA_SW_STTNGS_PRS);
    eval 'sub WDSM_RD_DATA () {0xd0;}' unless defined(&WDSM_RD_DATA);
    eval 'sub WDSM_RD_THRESHOLDS () {0xd1;}' unless defined(&WDSM_RD_THRESHOLDS);
    eval 'sub WDSM_ATTR_AUTOSAVE_EN () {0xd2;}' unless defined(&WDSM_ATTR_AUTOSAVE_EN);
    eval 'sub WDSM_SAVE_ATTR () {0xd3;}' unless defined(&WDSM_SAVE_ATTR);
    eval 'sub WDSM_EXEC_OFFL_IMM () {0xd4;}' unless defined(&WDSM_EXEC_OFFL_IMM);
    eval 'sub WDSM_RD_LOG () {0xd5;}' unless defined(&WDSM_RD_LOG);
    eval 'sub WDSM_ENABLE_OPS () {0xd8;}' unless defined(&WDSM_ENABLE_OPS);
    eval 'sub WDSM_DISABLE_OPS () {0xd9;}' unless defined(&WDSM_DISABLE_OPS);
    eval 'sub WDSM_STATUS () {0xda;}' unless defined(&WDSM_STATUS);
    eval 'sub WDSMART_CYL () {0xc24f;}' unless defined(&WDSMART_CYL);
    eval 'sub WDSC_PRIO_HIGH () { &__BIT(15);}' unless defined(&WDSC_PRIO_HIGH);
    eval 'sub WDSC_PRIO_ISOCHRONOUS () { &__BIT(14);}' unless defined(&WDSC_PRIO_ISOCHRONOUS);
    eval 'sub WDSC_PRIO_NORMAL () {0x;}' unless defined(&WDSC_PRIO_NORMAL);
    eval 'sub WDSD_IBM () {0xa0;}' unless defined(&WDSD_IBM);
    eval 'sub WDSD_CHS () {0x;}' unless defined(&WDSD_CHS);
    eval 'sub WDSD_LBA () {0x40;}' unless defined(&WDSD_LBA);
    eval 'sub WDSD_FUA () {0x80;}' unless defined(&WDSD_FUA);
    eval 'sub ATAPI_CHECK_POWER_MODE () {0xe5;}' unless defined(&ATAPI_CHECK_POWER_MODE);
    eval 'sub ATAPI_EXEC_DRIVE_DIAGS () {0x90;}' unless defined(&ATAPI_EXEC_DRIVE_DIAGS);
    eval 'sub ATAPI_IDLE_IMMEDIATE () {0xe1;}' unless defined(&ATAPI_IDLE_IMMEDIATE);
    eval 'sub ATAPI_NOP () {0x;}' unless defined(&ATAPI_NOP);
    eval 'sub ATAPI_PKT_CMD () {0xa0;}' unless defined(&ATAPI_PKT_CMD);
    eval 'sub ATAPI_IDENTIFY_DEVICE () {0xa1;}' unless defined(&ATAPI_IDENTIFY_DEVICE);
    eval 'sub ATAPI_SOFT_RESET () {0x8;}' unless defined(&ATAPI_SOFT_RESET);
    eval 'sub ATAPI_SLEEP () {0xe6;}' unless defined(&ATAPI_SLEEP);
    eval 'sub ATAPI_STANDBY_IMMEDIATE () {0xe0;}' unless defined(&ATAPI_STANDBY_IMMEDIATE);
    eval 'sub ATAPI_PKT_CMD_FTRE_DMA () {0x1;}' unless defined(&ATAPI_PKT_CMD_FTRE_DMA);
    eval 'sub ATAPI_PKT_CMD_FTRE_OVL () {0x2;}' unless defined(&ATAPI_PKT_CMD_FTRE_OVL);
    eval 'sub WDCI_CMD () {0x1;}' unless defined(&WDCI_CMD);
    eval 'sub WDCI_IN () {0x2;}' unless defined(&WDCI_IN);
    eval 'sub WDCI_RELEASE () {0x4;}' unless defined(&WDCI_RELEASE);
    eval 'sub PHASE_CMDOUT () {( &WDCS_DRQ |  &WDCI_CMD);}' unless defined(&PHASE_CMDOUT);
    eval 'sub PHASE_DATAIN () {( &WDCS_DRQ |  &WDCI_IN);}' unless defined(&PHASE_DATAIN);
    eval 'sub PHASE_DATAOUT () {( &WDCS_DRQ);}' unless defined(&PHASE_DATAOUT);
    eval 'sub PHASE_COMPLETED () {( &WDCI_IN |  &WDCI_CMD);}' unless defined(&PHASE_COMPLETED);
    eval 'sub PHASE_ABORTED () {(0);}' unless defined(&PHASE_ABORTED);
    eval 'sub WDC_CFG_CFA_MAGIC () {0x848a;}' unless defined(&WDC_CFG_CFA_MAGIC);
    eval 'sub WDC_CFG_ATAPI () {0x8000;}' unless defined(&WDC_CFG_ATAPI);
    eval 'sub ATA_CFG_REMOVABLE () {0x80;}' unless defined(&ATA_CFG_REMOVABLE);
    eval 'sub ATA_CFG_FIXED () {0x40;}' unless defined(&ATA_CFG_FIXED);
    eval 'sub ATAPI_CFG_TYPE_MASK () {0x1f00;}' unless defined(&ATAPI_CFG_TYPE_MASK);
    eval 'sub ATAPI_CFG_TYPE {
        my($x) = @_;
	    eval q(((($x) &  &ATAPI_CFG_TYPE_MASK) >> 8));
    }' unless defined(&ATAPI_CFG_TYPE);
    eval 'sub ATAPI_CFG_REMOV () {0x80;}' unless defined(&ATAPI_CFG_REMOV);
    eval 'sub ATAPI_CFG_DRQ_MASK () {0x60;}' unless defined(&ATAPI_CFG_DRQ_MASK);
    eval 'sub ATAPI_CFG_STD_DRQ () {0x;}' unless defined(&ATAPI_CFG_STD_DRQ);
    eval 'sub ATAPI_CFG_IRQ_DRQ () {0x20;}' unless defined(&ATAPI_CFG_IRQ_DRQ);
    eval 'sub ATAPI_CFG_ACCEL_DRQ () {0x40;}' unless defined(&ATAPI_CFG_ACCEL_DRQ);
    eval 'sub ATAPI_CFG_CMD_MASK () {0x3;}' unless defined(&ATAPI_CFG_CMD_MASK);
    eval 'sub ATAPI_CFG_CMD_12 () {0x;}' unless defined(&ATAPI_CFG_CMD_12);
    eval 'sub ATAPI_CFG_CMD_16 () {0x1;}' unless defined(&ATAPI_CFG_CMD_16);
    eval 'sub WDC_CAP_IORDY () {0x800;}' unless defined(&WDC_CAP_IORDY);
    eval 'sub WDC_CAP_IORDY_DSBL () {0x400;}' unless defined(&WDC_CAP_IORDY_DSBL);
    eval 'sub WDC_CAP_LBA () {0x200;}' unless defined(&WDC_CAP_LBA);
    eval 'sub WDC_CAP_DMA () {0x100;}' unless defined(&WDC_CAP_DMA);
    eval 'sub ATA_CAP_STBY () {0x2000;}' unless defined(&ATA_CAP_STBY);
    eval 'sub ATAPI_CAP_INTERL_DMA () {0x8000;}' unless defined(&ATAPI_CAP_INTERL_DMA);
    eval 'sub ATAPI_CAP_CMD_QUEUE () {0x4000;}' unless defined(&ATAPI_CAP_CMD_QUEUE);
    eval 'sub ATAPI_CAP_OVERLP () {0x2000;}' unless defined(&ATAPI_CAP_OVERLP);
    eval 'sub ATAPI_CAP_ATA_RST () {0x1000;}' unless defined(&ATAPI_CAP_ATA_RST);
    if((defined(&BYTE_ORDER) ? &BYTE_ORDER : undef) == (defined(&LITTLE_ENDIAN) ? &LITTLE_ENDIAN : undef)) {
    } else {
    }
    eval 'sub WDC_EXT_UDMA_MODES () {0x4;}' unless defined(&WDC_EXT_UDMA_MODES);
    eval 'sub WDC_EXT_MODES () {0x2;}' unless defined(&WDC_EXT_MODES);
    eval 'sub WDC_EXT_GEOM () {0x1;}' unless defined(&WDC_EXT_GEOM);
    eval 'sub WDC_MULTI_VALID () {0x100;}' unless defined(&WDC_MULTI_VALID);
    eval 'sub WDC_MULTI_MASK () {0xff;}' unless defined(&WDC_MULTI_MASK);
    if((defined(&BYTE_ORDER) ? &BYTE_ORDER : undef) == (defined(&LITTLE_ENDIAN) ? &LITTLE_ENDIAN : undef)) {
    } else {
    }
    eval 'sub WDC_QUEUE_DEPTH_MASK () {0x1f;}' unless defined(&WDC_QUEUE_DEPTH_MASK);
    eval 'sub SATA_SIGNAL_GEN1 () {0x2;}' unless defined(&SATA_SIGNAL_GEN1);
    eval 'sub SATA_SIGNAL_GEN2 () {0x4;}' unless defined(&SATA_SIGNAL_GEN2);
    eval 'sub SATA_SIGNAL_GEN3 () {0x8;}' unless defined(&SATA_SIGNAL_GEN3);
    eval 'sub SATA_NATIVE_CMDQ () {0x100;}' unless defined(&SATA_NATIVE_CMDQ);
    eval 'sub SATA_HOST_PWR_MGMT () {0x200;}' unless defined(&SATA_HOST_PWR_MGMT);
    eval 'sub SATA_PHY_EVNT_CNT () {0x400;}' unless defined(&SATA_PHY_EVNT_CNT);
    eval 'sub SATA_UNLOAD_W_NCQ () {0x800;}' unless defined(&SATA_UNLOAD_W_NCQ);
    eval 'sub SATA_NCQ_PRIO () {0x1000;}' unless defined(&SATA_NCQ_PRIO);
    eval 'sub SATA_NONZERO_OFFSETS () {0x2;}' unless defined(&SATA_NONZERO_OFFSETS);
    eval 'sub SATA_DMA_SETUP_AUTO () {0x4;}' unless defined(&SATA_DMA_SETUP_AUTO);
    eval 'sub SATA_DRIVE_PWR_MGMT () {0x8;}' unless defined(&SATA_DRIVE_PWR_MGMT);
    eval 'sub SATA_IN_ORDER_DATA () {0x10;}' unless defined(&SATA_IN_ORDER_DATA);
    eval 'sub SATA_SW_STTNGS_PRS () {0x40;}' unless defined(&SATA_SW_STTNGS_PRS);
    eval 'sub WDC_VER_ATA1 () {0x2;}' unless defined(&WDC_VER_ATA1);
    eval 'sub WDC_VER_ATA2 () {0x4;}' unless defined(&WDC_VER_ATA2);
    eval 'sub WDC_VER_ATA3 () {0x8;}' unless defined(&WDC_VER_ATA3);
    eval 'sub WDC_VER_ATA4 () {0x10;}' unless defined(&WDC_VER_ATA4);
    eval 'sub WDC_VER_ATA5 () {0x20;}' unless defined(&WDC_VER_ATA5);
    eval 'sub WDC_VER_ATA6 () {0x40;}' unless defined(&WDC_VER_ATA6);
    eval 'sub WDC_VER_ATA7 () {0x80;}' unless defined(&WDC_VER_ATA7);
    eval 'sub WDC_VER_ATA8 () {0x100;}' unless defined(&WDC_VER_ATA8);
    eval 'sub WDC_CMD1_NOP () {0x4000;}' unless defined(&WDC_CMD1_NOP);
    eval 'sub WDC_CMD1_RB () {0x2000;}' unless defined(&WDC_CMD1_RB);
    eval 'sub WDC_CMD1_WB () {0x1000;}' unless defined(&WDC_CMD1_WB);
    eval 'sub WDC_CMD1_HPA () {0x400;}' unless defined(&WDC_CMD1_HPA);
    eval 'sub WDC_CMD1_DVRST () {0x200;}' unless defined(&WDC_CMD1_DVRST);
    eval 'sub WDC_CMD1_SRV () {0x100;}' unless defined(&WDC_CMD1_SRV);
    eval 'sub WDC_CMD1_RLSE () {0x80;}' unless defined(&WDC_CMD1_RLSE);
    eval 'sub WDC_CMD1_AHEAD () {0x40;}' unless defined(&WDC_CMD1_AHEAD);
    eval 'sub WDC_CMD1_CACHE () {0x20;}' unless defined(&WDC_CMD1_CACHE);
    eval 'sub WDC_CMD1_PKT () {0x10;}' unless defined(&WDC_CMD1_PKT);
    eval 'sub WDC_CMD1_PM () {0x8;}' unless defined(&WDC_CMD1_PM);
    eval 'sub WDC_CMD1_REMOV () {0x4;}' unless defined(&WDC_CMD1_REMOV);
    eval 'sub WDC_CMD1_SEC () {0x2;}' unless defined(&WDC_CMD1_SEC);
    eval 'sub WDC_CMD1_SMART () {0x1;}' unless defined(&WDC_CMD1_SMART);
    eval 'sub ATA_CMD2_FCE () {0x2000;}' unless defined(&ATA_CMD2_FCE);
    eval 'sub WDC_CMD2_FC () {0x1000;}' unless defined(&WDC_CMD2_FC);
    eval 'sub WDC_CMD2_DCO () {0x800;}' unless defined(&WDC_CMD2_DCO);
    eval 'sub ATA_CMD2_LBA48 () {0x400;}' unless defined(&ATA_CMD2_LBA48);
    eval 'sub WDC_CMD2_AAM () {0x200;}' unless defined(&WDC_CMD2_AAM);
    eval 'sub WDC_CMD2_SM () {0x100;}' unless defined(&WDC_CMD2_SM);
    eval 'sub WDC_CMD2_SFREQ () {0x40;}' unless defined(&WDC_CMD2_SFREQ);
    eval 'sub WDC_CMD2_PUIS () {0x20;}' unless defined(&WDC_CMD2_PUIS);
    eval 'sub WDC_CMD2_RMSN () {0x10;}' unless defined(&WDC_CMD2_RMSN);
    eval 'sub ATA_CMD2_APM () {0x8;}' unless defined(&ATA_CMD2_APM);
    eval 'sub ATA_CMD2_CFA () {0x4;}' unless defined(&ATA_CMD2_CFA);
    eval 'sub ATA_CMD2_RWQ () {0x2;}' unless defined(&ATA_CMD2_RWQ);
    eval 'sub WDC_CMD2_DM () {0x1;}' unless defined(&WDC_CMD2_DM);
    eval 'sub ATA_CMDE_TLCONT () {0x1000;}' unless defined(&ATA_CMDE_TLCONT);
    eval 'sub ATA_CMDE_TL () {0x800;}' unless defined(&ATA_CMDE_TL);
    eval 'sub ATA_CMDE_URGW () {0x400;}' unless defined(&ATA_CMDE_URGW);
    eval 'sub ATA_CMDE_URGR () {0x200;}' unless defined(&ATA_CMDE_URGR);
    eval 'sub ATA_CMDE_WWN () {0x100;}' unless defined(&ATA_CMDE_WWN);
    eval 'sub ATA_CMDE_WQFE () {0x80;}' unless defined(&ATA_CMDE_WQFE);
    eval 'sub ATA_CMDE_WFE () {0x40;}' unless defined(&ATA_CMDE_WFE);
    eval 'sub ATA_CMDE_GPL () {0x20;}' unless defined(&ATA_CMDE_GPL);
    eval 'sub ATA_CMDE_STREAM () {0x10;}' unless defined(&ATA_CMDE_STREAM);
    eval 'sub ATA_CMDE_MCPTC () {0x8;}' unless defined(&ATA_CMDE_MCPTC);
    eval 'sub ATA_CMDE_MS () {0x4;}' unless defined(&ATA_CMDE_MS);
    eval 'sub ATA_CMDE_SST () {0x2;}' unless defined(&ATA_CMDE_SST);
    eval 'sub ATA_CMDE_SEL () {0x1;}' unless defined(&ATA_CMDE_SEL);
    if((defined(&BYTE_ORDER) ? &BYTE_ORDER : undef) == (defined(&LITTLE_ENDIAN) ? &LITTLE_ENDIAN : undef)) {
    } else {
    }
    eval 'sub ATA_SECSZ_VALID_MASK () {0xc000;}' unless defined(&ATA_SECSZ_VALID_MASK);
    eval 'sub ATA_SECSZ_VALID () {0x4000;}' unless defined(&ATA_SECSZ_VALID);
    eval 'sub ATA_SECSZ_LPS () {0x2000;}' unless defined(&ATA_SECSZ_LPS);
    eval 'sub ATA_SECSZ_LLS () {0x1000;}' unless defined(&ATA_SECSZ_LLS);
    eval 'sub ATA_SECSZ_LPS_SZMSK () {0xf;}' unless defined(&ATA_SECSZ_LPS_SZMSK);
    eval 'sub WDC_RMSN_SUPP_MASK () {0x3;}' unless defined(&WDC_RMSN_SUPP_MASK);
    eval 'sub WDC_RMSN_SUPP () {0x1;}' unless defined(&WDC_RMSN_SUPP);
    eval 'sub WDC_SEC_LEV_MAX () {0x100;}' unless defined(&WDC_SEC_LEV_MAX);
    eval 'sub WDC_SEC_ESE_SUPP () {0x20;}' unless defined(&WDC_SEC_ESE_SUPP);
    eval 'sub WDC_SEC_EXP () {0x10;}' unless defined(&WDC_SEC_EXP);
    eval 'sub WDC_SEC_FROZEN () {0x8;}' unless defined(&WDC_SEC_FROZEN);
    eval 'sub WDC_SEC_LOCKED () {0x4;}' unless defined(&WDC_SEC_LOCKED);
    eval 'sub WDC_SEC_EN () {0x2;}' unless defined(&WDC_SEC_EN);
    eval 'sub WDC_SEC_SUPP () {0x1;}' unless defined(&WDC_SEC_SUPP);
    eval 'sub ATA_CFA_MAX_MASK () {0xfff;}' unless defined(&ATA_CFA_MAX_MASK);
    eval 'sub ATA_CFA_MODE1_DIS () {0x1000;}' unless defined(&ATA_CFA_MODE1_DIS);
    eval 'sub ATA_CFA_MODE1_REQ () {0x2000;}' unless defined(&ATA_CFA_MODE1_REQ);
    eval 'sub ATA_CFA_WORD160 () {0x8000;}' unless defined(&ATA_CFA_WORD160);
    eval 'sub ATA_SUPPORT_DSM_TRIM () {0x1;}' unless defined(&ATA_SUPPORT_DSM_TRIM);
    eval 'sub ATA_LA_VALID_MASK () {0xc000;}' unless defined(&ATA_LA_VALID_MASK);
    eval 'sub ATA_LA_VALID () {0x4000;}' unless defined(&ATA_LA_VALID);
    eval 'sub ATA_LA_MASK () {0x3fff;}' unless defined(&ATA_LA_MASK);
    eval 'sub WDC_INTEGRITY_MAGIC_MASK () {0xff;}' unless defined(&WDC_INTEGRITY_MAGIC_MASK);
    eval 'sub WDC_INTEGRITY_MAGIC () {0xa5;}' unless defined(&WDC_INTEGRITY_MAGIC);
    eval 'sub WDSM_ATTR_ADVISORY () {1;}' unless defined(&WDSM_ATTR_ADVISORY);
    eval 'sub WDSM_ATTR_COLLECTIVE () {2;}' unless defined(&WDSM_ATTR_COLLECTIVE);
}
1;
