/* Generated automatically by the program `gencodes'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CODES_H
#define GCC_INSN_CODES_H

enum insn_code {
  CODE_FOR_nothing = 0,

  CODE_FOR_x86_fnstsw_1 = 47,
  CODE_FOR_x86_sahf_1 = 48,
  CODE_FOR_kmovw = 84,
  CODE_FOR_movsi_insv_1 = 109,
#define CODE_FOR_movdi_insv_1 CODE_FOR_nothing
  CODE_FOR_swapxf = 119,
#define CODE_FOR_zero_extendqidi2 CODE_FOR_nothing
#define CODE_FOR_zero_extendhidi2 CODE_FOR_nothing
  CODE_FOR_zero_extendqisi2_and = 123,
  CODE_FOR_zero_extendhisi2_and = 124,
  CODE_FOR_zero_extendqihi2_and = 127,
  CODE_FOR_extendsidi2_1 = 129,
#define CODE_FOR_extendqidi2 CODE_FOR_nothing
#define CODE_FOR_extendhidi2 CODE_FOR_nothing
  CODE_FOR_extendhisi2 = 130,
  CODE_FOR_extendqisi2 = 131,
  CODE_FOR_extendqihi2 = 132,
  CODE_FOR_truncxfsf2_i387_noop = 146,
  CODE_FOR_truncxfdf2_i387_noop = 147,
  CODE_FOR_fix_truncsfsi_sse = 152,
#define CODE_FOR_fix_truncsfdi_sse CODE_FOR_nothing
  CODE_FOR_fix_truncdfsi_sse = 153,
#define CODE_FOR_fix_truncdfdi_sse CODE_FOR_nothing
  CODE_FOR_fix_trunchi_fisttp_i387_1 = 154,
  CODE_FOR_fix_truncsi_fisttp_i387_1 = 155,
  CODE_FOR_fix_truncdi_fisttp_i387_1 = 156,
  CODE_FOR_fix_trunchi_i387_fisttp = 157,
  CODE_FOR_fix_truncsi_i387_fisttp = 158,
  CODE_FOR_fix_truncdi_i387_fisttp = 159,
  CODE_FOR_fix_trunchi_i387_fisttp_with_temp = 160,
  CODE_FOR_fix_truncsi_i387_fisttp_with_temp = 161,
  CODE_FOR_fix_truncdi_i387_fisttp_with_temp = 162,
  CODE_FOR_fix_truncdi_i387 = 166,
  CODE_FOR_fix_truncdi_i387_with_temp = 167,
  CODE_FOR_fix_trunchi_i387 = 168,
  CODE_FOR_fix_truncsi_i387 = 169,
  CODE_FOR_fix_trunchi_i387_with_temp = 170,
  CODE_FOR_fix_truncsi_i387_with_temp = 171,
  CODE_FOR_x86_fnstcw_1 = 172,
  CODE_FOR_x86_fldcw_1 = 173,
  CODE_FOR_floathisf2 = 174,
  CODE_FOR_floathidf2 = 175,
  CODE_FOR_floathixf2 = 176,
  CODE_FOR_floatsixf2 = 177,
  CODE_FOR_floatdixf2 = 178,
  CODE_FOR_floatdisf2_i387_with_xmm = 185,
  CODE_FOR_floatdidf2_i387_with_xmm = 186,
  CODE_FOR_floatdixf2_i387_with_xmm = 187,
  CODE_FOR_addqi3_cc = 196,
#define CODE_FOR_addsi_1_zext CODE_FOR_nothing
  CODE_FOR_addqi_ext_1 = 217,
  CODE_FOR_adcxsi3 = 263,
  CODE_FOR_adcxdi3 = 264,
  CODE_FOR_divmodsi4_1 = 286,
#define CODE_FOR_divmoddi4_1 CODE_FOR_nothing
  CODE_FOR_divmodhiqi3 = 291,
  CODE_FOR_udivmodsi4_1 = 292,
#define CODE_FOR_udivmoddi4_1 CODE_FOR_nothing
  CODE_FOR_udivmodhiqi3 = 297,
  CODE_FOR_kandnqi = 317,
  CODE_FOR_kandnhi = 318,
  CODE_FOR_andqi_ext_0 = 324,
  CODE_FOR_kxnorqi = 346,
  CODE_FOR_kxnorhi = 347,
  CODE_FOR_kortestzhi = 348,
  CODE_FOR_kortestchi = 349,
  CODE_FOR_kunpckhi = 350,
  CODE_FOR_copysignsf3_const = 402,
  CODE_FOR_copysigndf3_const = 403,
  CODE_FOR_copysigntf3_const = 404,
  CODE_FOR_copysignsf3_var = 405,
  CODE_FOR_copysigndf3_var = 406,
  CODE_FOR_copysigntf3_var = 407,
#define CODE_FOR_x86_64_shld CODE_FOR_nothing
  CODE_FOR_x86_shld = 417,
#define CODE_FOR_x86_64_shrd CODE_FOR_nothing
  CODE_FOR_x86_shrd = 440,
#define CODE_FOR_ashrdi3_cvt CODE_FOR_nothing
  CODE_FOR_ashrsi3_cvt = 441,
  CODE_FOR_ix86_rotldi3_doubleword = 474,
#define CODE_FOR_ix86_rotlti3_doubleword CODE_FOR_nothing
  CODE_FOR_ix86_rotrdi3_doubleword = 475,
#define CODE_FOR_ix86_rotrti3_doubleword CODE_FOR_nothing
  CODE_FOR_setcc_sf_sse = 493,
  CODE_FOR_setcc_df_sse = 494,
  CODE_FOR_jump = 535,
  CODE_FOR_blockage = 552,
  CODE_FOR_prologue_use = 554,
  CODE_FOR_simple_return_internal = 555,
  CODE_FOR_simple_return_internal_long = 556,
  CODE_FOR_simple_return_pop_internal = 557,
  CODE_FOR_simple_return_indirect_internal = 558,
  CODE_FOR_nop = 559,
  CODE_FOR_nops = 560,
  CODE_FOR_pad = 561,
  CODE_FOR_set_got = 562,
  CODE_FOR_set_got_labelled = 563,
#define CODE_FOR_set_got_rex64 CODE_FOR_nothing
#define CODE_FOR_set_rip_rex64 CODE_FOR_nothing
  CODE_FOR_set_got_offset_rex64 = 564,
  CODE_FOR_eh_return_internal = 565,
  CODE_FOR_leave = 566,
#define CODE_FOR_leave_rex64 CODE_FOR_nothing
  CODE_FOR_split_stack_return = 567,
  CODE_FOR_ffssi2_no_cmove = 568,
  CODE_FOR_bmi_bextr_si = 582,
#define CODE_FOR_bmi_bextr_di CODE_FOR_nothing
  CODE_FOR_bmi2_bzhi_si3 = 586,
#define CODE_FOR_bmi2_bzhi_di3 CODE_FOR_nothing
  CODE_FOR_bmi2_pdep_si3 = 587,
#define CODE_FOR_bmi2_pdep_di3 CODE_FOR_nothing
  CODE_FOR_bmi2_pext_si3 = 588,
#define CODE_FOR_bmi2_pext_di3 CODE_FOR_nothing
  CODE_FOR_tbm_bextri_si = 589,
#define CODE_FOR_tbm_bextri_di CODE_FOR_nothing
#define CODE_FOR_bsr_rex64 CODE_FOR_nothing
  CODE_FOR_bsr = 599,
  CODE_FOR_bswaphi_lowpart = 609,
  CODE_FOR_paritydi2_cmp = 610,
  CODE_FOR_paritysi2_cmp = 611,
#define CODE_FOR_tls_initial_exec_64_sun CODE_FOR_nothing
  CODE_FOR_truncxfsf2_i387_noop_unspec = 663,
  CODE_FOR_truncxfdf2_i387_noop_unspec = 664,
  CODE_FOR_sqrtxf2 = 665,
  CODE_FOR_sqrt_extendsfxf2_i387 = 666,
  CODE_FOR_sqrt_extenddfxf2_i387 = 667,
  CODE_FOR_fpremxf4_i387 = 671,
  CODE_FOR_fprem1xf4_i387 = 672,
  CODE_FOR_sincosxf3 = 679,
  CODE_FOR_sincos_extendsfxf3_i387 = 680,
  CODE_FOR_sincos_extenddfxf3_i387 = 681,
  CODE_FOR_fptanxf4_i387 = 682,
  CODE_FOR_fptan_extendsfxf4_i387 = 683,
  CODE_FOR_fptan_extenddfxf4_i387 = 684,
  CODE_FOR_fpatan_extendsfxf3_i387 = 686,
  CODE_FOR_fpatan_extenddfxf3_i387 = 687,
  CODE_FOR_fyl2xxf3_i387 = 688,
  CODE_FOR_fyl2x_extendsfxf3_i387 = 689,
  CODE_FOR_fyl2x_extenddfxf3_i387 = 690,
  CODE_FOR_fyl2xp1xf3_i387 = 691,
  CODE_FOR_fyl2xp1_extendsfxf3_i387 = 692,
  CODE_FOR_fyl2xp1_extenddfxf3_i387 = 693,
  CODE_FOR_fxtractxf3_i387 = 694,
  CODE_FOR_fxtract_extendsfxf3_i387 = 695,
  CODE_FOR_fxtract_extenddfxf3_i387 = 696,
  CODE_FOR_fscalexf4_i387 = 698,
  CODE_FOR_sse4_1_roundsf2 = 699,
  CODE_FOR_sse4_1_rounddf2 = 700,
  CODE_FOR_rintxf2 = 701,
  CODE_FOR_fistdi2 = 703,
  CODE_FOR_fistdi2_with_temp = 704,
  CODE_FOR_fisthi2 = 707,
  CODE_FOR_fistsi2 = 708,
  CODE_FOR_fisthi2_with_temp = 709,
  CODE_FOR_fistsi2_with_temp = 710,
  CODE_FOR_frndintxf2_floor = 711,
  CODE_FOR_frndintxf2_ceil = 712,
  CODE_FOR_frndintxf2_trunc = 713,
  CODE_FOR_frndintxf2_floor_i387 = 714,
  CODE_FOR_frndintxf2_ceil_i387 = 715,
  CODE_FOR_frndintxf2_trunc_i387 = 716,
  CODE_FOR_frndintxf2_mask_pm = 717,
  CODE_FOR_frndintxf2_mask_pm_i387 = 718,
  CODE_FOR_fistdi2_floor = 725,
  CODE_FOR_fistdi2_ceil = 726,
  CODE_FOR_fistdi2_floor_with_temp = 727,
  CODE_FOR_fistdi2_ceil_with_temp = 728,
  CODE_FOR_fisthi2_floor = 729,
  CODE_FOR_fisthi2_ceil = 730,
  CODE_FOR_fistsi2_floor = 731,
  CODE_FOR_fistsi2_ceil = 732,
  CODE_FOR_fisthi2_floor_with_temp = 733,
  CODE_FOR_fisthi2_ceil_with_temp = 734,
  CODE_FOR_fistsi2_floor_with_temp = 735,
  CODE_FOR_fistsi2_ceil_with_temp = 736,
  CODE_FOR_fxamsf2_i387 = 737,
  CODE_FOR_fxamdf2_i387 = 738,
  CODE_FOR_fxamxf2_i387 = 739,
  CODE_FOR_fxamsf2_i387_with_temp = 740,
  CODE_FOR_fxamdf2_i387_with_temp = 741,
  CODE_FOR_movmsk_df = 742,
  CODE_FOR_cld = 743,
  CODE_FOR_smaxsf3 = 781,
  CODE_FOR_sminsf3 = 782,
  CODE_FOR_smaxdf3 = 783,
  CODE_FOR_smindf3 = 784,
  CODE_FOR_pro_epilogue_adjust_stack_si_add = 789,
  CODE_FOR_pro_epilogue_adjust_stack_di_add = 790,
  CODE_FOR_pro_epilogue_adjust_stack_si_sub = 791,
  CODE_FOR_pro_epilogue_adjust_stack_di_sub = 792,
  CODE_FOR_allocate_stack_worker_probe_si = 793,
  CODE_FOR_allocate_stack_worker_probe_di = 794,
  CODE_FOR_adjust_stack_and_probesi = 795,
  CODE_FOR_adjust_stack_and_probedi = 796,
  CODE_FOR_probe_stack_rangesi = 797,
  CODE_FOR_probe_stack_rangedi = 798,
#define CODE_FOR_nonlocal_goto_receiver CODE_FOR_nothing
  CODE_FOR_trap = 799,
  CODE_FOR_stack_protect_set_si = 804,
  CODE_FOR_stack_protect_set_di = 805,
  CODE_FOR_stack_tls_protect_set_si = 806,
  CODE_FOR_stack_tls_protect_set_di = 807,
  CODE_FOR_stack_protect_test_si = 808,
  CODE_FOR_stack_protect_test_di = 809,
  CODE_FOR_stack_tls_protect_test_si = 810,
  CODE_FOR_stack_tls_protect_test_di = 811,
  CODE_FOR_sse4_2_crc32qi = 812,
  CODE_FOR_sse4_2_crc32hi = 813,
  CODE_FOR_sse4_2_crc32si = 814,
#define CODE_FOR_sse4_2_crc32di CODE_FOR_nothing
  CODE_FOR_rdpmc = 815,
#define CODE_FOR_rdpmc_rex64 CODE_FOR_nothing
  CODE_FOR_rdtsc = 816,
#define CODE_FOR_rdtsc_rex64 CODE_FOR_nothing
  CODE_FOR_rdtscp = 817,
#define CODE_FOR_rdtscp_rex64 CODE_FOR_nothing
  CODE_FOR_fxsave = 818,
#define CODE_FOR_fxsave64 CODE_FOR_nothing
  CODE_FOR_fxrstor = 819,
#define CODE_FOR_fxrstor64 CODE_FOR_nothing
  CODE_FOR_xsave = 820,
  CODE_FOR_xsaveopt = 821,
#define CODE_FOR_xsave_rex64 CODE_FOR_nothing
#define CODE_FOR_xsaveopt_rex64 CODE_FOR_nothing
#define CODE_FOR_xsave64 CODE_FOR_nothing
#define CODE_FOR_xsaveopt64 CODE_FOR_nothing
  CODE_FOR_xrstor = 822,
#define CODE_FOR_xrstor_rex64 CODE_FOR_nothing
#define CODE_FOR_xrstor64 CODE_FOR_nothing
  CODE_FOR_fnstenv = 823,
  CODE_FOR_fldenv = 824,
  CODE_FOR_fnstsw = 825,
  CODE_FOR_fnclex = 826,
  CODE_FOR_lwp_slwpcbsi = 829,
  CODE_FOR_lwp_slwpcbdi = 830,
#define CODE_FOR_rdfsbasesi CODE_FOR_nothing
#define CODE_FOR_rdgsbasesi CODE_FOR_nothing
#define CODE_FOR_rdfsbasedi CODE_FOR_nothing
#define CODE_FOR_rdgsbasedi CODE_FOR_nothing
#define CODE_FOR_wrfsbasesi CODE_FOR_nothing
#define CODE_FOR_wrgsbasesi CODE_FOR_nothing
#define CODE_FOR_wrfsbasedi CODE_FOR_nothing
#define CODE_FOR_wrgsbasedi CODE_FOR_nothing
  CODE_FOR_rdrandhi_1 = 833,
  CODE_FOR_rdrandsi_1 = 834,
#define CODE_FOR_rdranddi_1 CODE_FOR_nothing
  CODE_FOR_rdseedhi_1 = 835,
  CODE_FOR_rdseedsi_1 = 836,
#define CODE_FOR_rdseeddi_1 CODE_FOR_nothing
  CODE_FOR_xbegin_1 = 838,
  CODE_FOR_xend = 839,
  CODE_FOR_xabort = 840,
  CODE_FOR_xtest_1 = 841,
  CODE_FOR_sse_movntq = 847,
  CODE_FOR_mmx_rcpv2sf2 = 855,
  CODE_FOR_mmx_rcpit1v2sf3 = 856,
  CODE_FOR_mmx_rcpit2v2sf3 = 857,
  CODE_FOR_mmx_rsqrtv2sf2 = 858,
  CODE_FOR_mmx_rsqit1v2sf3 = 859,
  CODE_FOR_mmx_haddv2sf3 = 860,
  CODE_FOR_mmx_hsubv2sf3 = 861,
  CODE_FOR_mmx_addsubv2sf3 = 862,
  CODE_FOR_mmx_gtv2sf3 = 864,
  CODE_FOR_mmx_gev2sf3 = 865,
  CODE_FOR_mmx_pf2id = 866,
  CODE_FOR_mmx_pf2iw = 867,
  CODE_FOR_mmx_pi2fw = 868,
  CODE_FOR_mmx_floatv2si2 = 869,
  CODE_FOR_mmx_pswapdv2sf2 = 870,
  CODE_FOR_mmx_ashrv4hi3 = 901,
  CODE_FOR_mmx_ashrv2si3 = 902,
  CODE_FOR_mmx_ashlv4hi3 = 903,
  CODE_FOR_mmx_lshrv4hi3 = 904,
  CODE_FOR_mmx_ashlv2si3 = 905,
  CODE_FOR_mmx_lshrv2si3 = 906,
  CODE_FOR_mmx_ashlv1di3 = 907,
  CODE_FOR_mmx_lshrv1di3 = 908,
  CODE_FOR_mmx_gtv8qi3 = 912,
  CODE_FOR_mmx_gtv4hi3 = 913,
  CODE_FOR_mmx_gtv2si3 = 914,
  CODE_FOR_mmx_andnotv8qi3 = 915,
  CODE_FOR_mmx_andnotv4hi3 = 916,
  CODE_FOR_mmx_andnotv2si3 = 917,
  CODE_FOR_mmx_packsswb = 927,
  CODE_FOR_mmx_packssdw = 928,
  CODE_FOR_mmx_packuswb = 929,
  CODE_FOR_mmx_punpckhbw = 930,
  CODE_FOR_mmx_punpcklbw = 931,
  CODE_FOR_mmx_punpckhwd = 932,
  CODE_FOR_mmx_punpcklwd = 933,
  CODE_FOR_mmx_punpckhdq = 934,
  CODE_FOR_mmx_punpckldq = 935,
  CODE_FOR_mmx_pextrw = 937,
  CODE_FOR_mmx_pshufw_1 = 938,
  CODE_FOR_mmx_pswapdv2si2 = 939,
  CODE_FOR_mmx_psadbw = 947,
  CODE_FOR_mmx_pmovmskb = 948,
  CODE_FOR_avx512f_loadv16si_mask = 973,
  CODE_FOR_avx512f_loadv16sf_mask = 974,
  CODE_FOR_avx512f_loadv8di_mask = 975,
  CODE_FOR_avx512f_loadv8df_mask = 976,
  CODE_FOR_avx512f_blendmv16si = 977,
  CODE_FOR_avx512f_blendmv16sf = 978,
  CODE_FOR_avx512f_blendmv8di = 979,
  CODE_FOR_avx512f_blendmv8df = 980,
  CODE_FOR_avx512f_storev16si_mask = 981,
  CODE_FOR_avx512f_storev16sf_mask = 982,
  CODE_FOR_avx512f_storev8di_mask = 983,
  CODE_FOR_avx512f_storev8df_mask = 984,
  CODE_FOR_sse2_movq128 = 985,
  CODE_FOR_movdi_to_sse = 986,
  CODE_FOR_avx512f_storeups512 = 995,
  CODE_FOR_avx_storeups256 = 996,
  CODE_FOR_sse_storeups = 997,
  CODE_FOR_avx512f_storeupd512 = 998,
  CODE_FOR_avx_storeupd256 = 999,
  CODE_FOR_sse2_storeupd = 1000,
  CODE_FOR_avx512f_storeups512_mask = 1001,
  CODE_FOR_avx512f_storeupd512_mask = 1002,
  CODE_FOR_avx_storedquv32qi = 1009,
  CODE_FOR_sse2_storedquv16qi = 1010,
  CODE_FOR_avx512f_storedquv16si = 1011,
  CODE_FOR_avx512f_storedquv8di = 1012,
  CODE_FOR_avx512f_storedquv16si_mask = 1013,
  CODE_FOR_avx512f_storedquv8di_mask = 1014,
  CODE_FOR_avx_lddqu256 = 1015,
  CODE_FOR_sse3_lddqu = 1016,
  CODE_FOR_sse2_movntisi = 1017,
#define CODE_FOR_sse2_movntidi CODE_FOR_nothing
  CODE_FOR_avx512f_movntv16sf = 1018,
  CODE_FOR_avx_movntv8sf = 1019,
  CODE_FOR_sse_movntv4sf = 1020,
  CODE_FOR_avx512f_movntv8df = 1021,
  CODE_FOR_avx_movntv4df = 1022,
  CODE_FOR_sse2_movntv2df = 1023,
  CODE_FOR_avx512f_movntv8di = 1024,
  CODE_FOR_avx_movntv4di = 1025,
  CODE_FOR_sse2_movntv2di = 1026,
  CODE_FOR_sse_vmaddv4sf3 = 1081,
  CODE_FOR_sse_vmaddv4sf3_round = 1082,
  CODE_FOR_sse_vmsubv4sf3 = 1083,
  CODE_FOR_sse_vmsubv4sf3_round = 1084,
  CODE_FOR_sse2_vmaddv2df3 = 1085,
  CODE_FOR_sse2_vmaddv2df3_round = 1086,
  CODE_FOR_sse2_vmsubv2df3 = 1087,
  CODE_FOR_sse2_vmsubv2df3_round = 1088,
  CODE_FOR_sse_vmmulv4sf3 = 1113,
  CODE_FOR_sse_vmmulv4sf3_round = 1114,
  CODE_FOR_sse_vmdivv4sf3 = 1115,
  CODE_FOR_sse_vmdivv4sf3_round = 1116,
  CODE_FOR_sse2_vmmulv2df3 = 1117,
  CODE_FOR_sse2_vmmulv2df3_round = 1118,
  CODE_FOR_sse2_vmdivv2df3 = 1119,
  CODE_FOR_sse2_vmdivv2df3_round = 1120,
  CODE_FOR_avx512f_divv16sf3 = 1121,
  CODE_FOR_avx512f_divv16sf3_round = 1122,
  CODE_FOR_avx512f_divv16sf3_mask = 1123,
  CODE_FOR_avx512f_divv16sf3_mask_round = 1124,
  CODE_FOR_avx_divv8sf3 = 1125,
#define CODE_FOR_avx_divv8sf3_round CODE_FOR_nothing
#define CODE_FOR_avx_divv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_avx_divv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_sse_divv4sf3 = 1126,
#define CODE_FOR_sse_divv4sf3_round CODE_FOR_nothing
#define CODE_FOR_sse_divv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_sse_divv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_divv8df3 = 1127,
  CODE_FOR_avx512f_divv8df3_round = 1128,
  CODE_FOR_avx512f_divv8df3_mask = 1129,
  CODE_FOR_avx512f_divv8df3_mask_round = 1130,
  CODE_FOR_avx_divv4df3 = 1131,
#define CODE_FOR_avx_divv4df3_round CODE_FOR_nothing
#define CODE_FOR_avx_divv4df3_mask CODE_FOR_nothing
#define CODE_FOR_avx_divv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_sse2_divv2df3 = 1132,
#define CODE_FOR_sse2_divv2df3_round CODE_FOR_nothing
#define CODE_FOR_sse2_divv2df3_mask CODE_FOR_nothing
#define CODE_FOR_sse2_divv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_avx_rcpv8sf2 = 1133,
  CODE_FOR_sse_rcpv4sf2 = 1134,
  CODE_FOR_sse_vmrcpv4sf2 = 1135,
  CODE_FOR_rcp14v16sf_mask = 1137,
  CODE_FOR_rcp14v8df_mask = 1139,
  CODE_FOR_srcp14v4sf = 1140,
  CODE_FOR_srcp14v2df = 1141,
  CODE_FOR_avx512f_sqrtv16sf2 = 1142,
  CODE_FOR_avx512f_sqrtv16sf2_round = 1143,
  CODE_FOR_avx512f_sqrtv16sf2_mask = 1144,
  CODE_FOR_avx512f_sqrtv16sf2_mask_round = 1145,
  CODE_FOR_avx_sqrtv8sf2 = 1146,
#define CODE_FOR_avx_sqrtv8sf2_round CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv8sf2_mask CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv8sf2_mask_round CODE_FOR_nothing
  CODE_FOR_sse_sqrtv4sf2 = 1147,
#define CODE_FOR_sse_sqrtv4sf2_round CODE_FOR_nothing
#define CODE_FOR_sse_sqrtv4sf2_mask CODE_FOR_nothing
#define CODE_FOR_sse_sqrtv4sf2_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_sqrtv8df2 = 1148,
  CODE_FOR_avx512f_sqrtv8df2_round = 1149,
  CODE_FOR_avx512f_sqrtv8df2_mask = 1150,
  CODE_FOR_avx512f_sqrtv8df2_mask_round = 1151,
  CODE_FOR_avx_sqrtv4df2 = 1152,
#define CODE_FOR_avx_sqrtv4df2_round CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv4df2_mask CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv4df2_mask_round CODE_FOR_nothing
  CODE_FOR_sse2_sqrtv2df2 = 1153,
#define CODE_FOR_sse2_sqrtv2df2_round CODE_FOR_nothing
#define CODE_FOR_sse2_sqrtv2df2_mask CODE_FOR_nothing
#define CODE_FOR_sse2_sqrtv2df2_mask_round CODE_FOR_nothing
  CODE_FOR_sse_vmsqrtv4sf2 = 1154,
  CODE_FOR_sse_vmsqrtv4sf2_round = 1155,
  CODE_FOR_sse2_vmsqrtv2df2 = 1156,
  CODE_FOR_sse2_vmsqrtv2df2_round = 1157,
  CODE_FOR_avx_rsqrtv8sf2 = 1158,
  CODE_FOR_sse_rsqrtv4sf2 = 1159,
  CODE_FOR_rsqrt14v16sf_mask = 1161,
  CODE_FOR_rsqrt14v8df_mask = 1163,
  CODE_FOR_rsqrt14v4sf = 1164,
  CODE_FOR_rsqrt14v2df = 1165,
  CODE_FOR_sse_vmrsqrtv4sf2 = 1166,
  CODE_FOR_sse_vmsmaxv4sf3 = 1239,
  CODE_FOR_sse_vmsmaxv4sf3_round = 1240,
  CODE_FOR_sse_vmsminv4sf3 = 1241,
  CODE_FOR_sse_vmsminv4sf3_round = 1242,
  CODE_FOR_sse2_vmsmaxv2df3 = 1243,
  CODE_FOR_sse2_vmsmaxv2df3_round = 1244,
  CODE_FOR_sse2_vmsminv2df3 = 1245,
  CODE_FOR_sse2_vmsminv2df3_round = 1246,
  CODE_FOR_avx_addsubv4df3 = 1259,
  CODE_FOR_sse3_addsubv2df3 = 1260,
  CODE_FOR_avx_addsubv8sf3 = 1261,
  CODE_FOR_sse3_addsubv4sf3 = 1262,
  CODE_FOR_avx_haddv4df3 = 1263,
  CODE_FOR_avx_hsubv4df3 = 1264,
  CODE_FOR_sse3_hsubv2df3 = 1266,
  CODE_FOR_avx_haddv8sf3 = 1269,
  CODE_FOR_avx_hsubv8sf3 = 1270,
  CODE_FOR_sse3_haddv4sf3 = 1271,
  CODE_FOR_sse3_hsubv4sf3 = 1272,
  CODE_FOR_avx_cmpv8sf3 = 1273,
  CODE_FOR_avx_cmpv4sf3 = 1274,
  CODE_FOR_avx_cmpv4df3 = 1275,
  CODE_FOR_avx_cmpv2df3 = 1276,
  CODE_FOR_avx_vmcmpv4sf3 = 1277,
  CODE_FOR_avx_vmcmpv2df3 = 1278,
  CODE_FOR_avx_maskcmpv8sf3 = 1283,
  CODE_FOR_sse_maskcmpv4sf3 = 1284,
  CODE_FOR_avx_maskcmpv4df3 = 1285,
  CODE_FOR_sse2_maskcmpv2df3 = 1286,
  CODE_FOR_sse_vmmaskcmpv4sf3 = 1287,
  CODE_FOR_sse2_vmmaskcmpv2df3 = 1288,
  CODE_FOR_avx512f_cmpv16si3 = 1289,
  CODE_FOR_avx512f_cmpv16si3_mask = 1290,
#define CODE_FOR_avx512f_cmpv16si3_round CODE_FOR_nothing
#define CODE_FOR_avx512f_cmpv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_cmpv16sf3 = 1291,
  CODE_FOR_avx512f_cmpv16sf3_mask = 1292,
  CODE_FOR_avx512f_cmpv16sf3_round = 1293,
  CODE_FOR_avx512f_cmpv16sf3_mask_round = 1294,
  CODE_FOR_avx512f_cmpv8di3 = 1295,
  CODE_FOR_avx512f_cmpv8di3_mask = 1296,
#define CODE_FOR_avx512f_cmpv8di3_round CODE_FOR_nothing
#define CODE_FOR_avx512f_cmpv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_cmpv8df3 = 1297,
  CODE_FOR_avx512f_cmpv8df3_mask = 1298,
  CODE_FOR_avx512f_cmpv8df3_round = 1299,
  CODE_FOR_avx512f_cmpv8df3_mask_round = 1300,
  CODE_FOR_avx512f_ucmpv16si3 = 1301,
  CODE_FOR_avx512f_ucmpv16si3_mask = 1302,
  CODE_FOR_avx512f_ucmpv8di3 = 1303,
  CODE_FOR_avx512f_ucmpv8di3_mask = 1304,
  CODE_FOR_avx512f_vmcmpv4sf3 = 1305,
  CODE_FOR_avx512f_vmcmpv4sf3_round = 1306,
  CODE_FOR_avx512f_vmcmpv2df3 = 1307,
  CODE_FOR_avx512f_vmcmpv2df3_round = 1308,
  CODE_FOR_avx512f_vmcmpv4sf3_mask = 1309,
  CODE_FOR_avx512f_vmcmpv4sf3_mask_round = 1310,
  CODE_FOR_avx512f_vmcmpv2df3_mask = 1311,
  CODE_FOR_avx512f_vmcmpv2df3_mask_round = 1312,
  CODE_FOR_avx512f_maskcmpv16sf3 = 1313,
  CODE_FOR_avx512f_maskcmpv8sf3 = 1314,
  CODE_FOR_avx512f_maskcmpv4sf3 = 1315,
  CODE_FOR_avx512f_maskcmpv8df3 = 1316,
  CODE_FOR_avx512f_maskcmpv4df3 = 1317,
  CODE_FOR_avx512f_maskcmpv2df3 = 1318,
  CODE_FOR_sse_comi = 1319,
  CODE_FOR_sse_comi_round = 1320,
  CODE_FOR_sse2_comi = 1321,
  CODE_FOR_sse2_comi_round = 1322,
  CODE_FOR_sse_ucomi = 1323,
  CODE_FOR_sse_ucomi_round = 1324,
  CODE_FOR_sse2_ucomi = 1325,
  CODE_FOR_sse2_ucomi_round = 1326,
  CODE_FOR_avx512f_andnotv16sf3 = 1327,
  CODE_FOR_avx_andnotv8sf3 = 1328,
  CODE_FOR_sse_andnotv4sf3 = 1329,
  CODE_FOR_avx512f_andnotv8df3 = 1330,
  CODE_FOR_avx_andnotv4df3 = 1331,
  CODE_FOR_sse2_andnotv2df3 = 1332,
  CODE_FOR_avx512f_andv16sf = 1363,
  CODE_FOR_avx512f_xorv16sf = 1364,
  CODE_FOR_avx512f_andv8df = 1365,
  CODE_FOR_avx512f_xorv8df = 1366,
#define CODE_FOR_fma_fmadd_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmadd_v16sf_maskz_1 = 1375,
  CODE_FOR_fma_fmadd_v16sf_maskz_1_round = 1376,
  CODE_FOR_fma_fmadd_v8df_maskz_1 = 1379,
  CODE_FOR_fma_fmadd_v8df_maskz_1_round = 1380,
  CODE_FOR_avx512f_fmadd_v16sf_mask = 1381,
  CODE_FOR_avx512f_fmadd_v16sf_mask_round = 1382,
  CODE_FOR_avx512f_fmadd_v8df_mask = 1383,
  CODE_FOR_avx512f_fmadd_v8df_mask_round = 1384,
  CODE_FOR_avx512f_fmadd_v16sf_mask3 = 1385,
  CODE_FOR_avx512f_fmadd_v16sf_mask3_round = 1386,
  CODE_FOR_avx512f_fmadd_v8df_mask3 = 1387,
  CODE_FOR_avx512f_fmadd_v8df_mask3_round = 1388,
#define CODE_FOR_fma_fmsub_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmsub_v16sf_maskz_1 = 1397,
  CODE_FOR_fma_fmsub_v16sf_maskz_1_round = 1398,
  CODE_FOR_fma_fmsub_v8df_maskz_1 = 1401,
  CODE_FOR_fma_fmsub_v8df_maskz_1_round = 1402,
  CODE_FOR_avx512f_fmsub_v16sf_mask = 1403,
  CODE_FOR_avx512f_fmsub_v16sf_mask_round = 1404,
  CODE_FOR_avx512f_fmsub_v8df_mask = 1405,
  CODE_FOR_avx512f_fmsub_v8df_mask_round = 1406,
  CODE_FOR_avx512f_fmsub_v16sf_mask3 = 1407,
  CODE_FOR_avx512f_fmsub_v16sf_mask3_round = 1408,
  CODE_FOR_avx512f_fmsub_v8df_mask3 = 1409,
  CODE_FOR_avx512f_fmsub_v8df_mask3_round = 1410,
#define CODE_FOR_fma_fnmadd_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fnmadd_v16sf_maskz_1 = 1419,
  CODE_FOR_fma_fnmadd_v16sf_maskz_1_round = 1420,
  CODE_FOR_fma_fnmadd_v8df_maskz_1 = 1423,
  CODE_FOR_fma_fnmadd_v8df_maskz_1_round = 1424,
  CODE_FOR_avx512f_fnmadd_v16sf_mask = 1425,
  CODE_FOR_avx512f_fnmadd_v16sf_mask_round = 1426,
  CODE_FOR_avx512f_fnmadd_v8df_mask = 1427,
  CODE_FOR_avx512f_fnmadd_v8df_mask_round = 1428,
  CODE_FOR_avx512f_fnmadd_v16sf_mask3 = 1429,
  CODE_FOR_avx512f_fnmadd_v16sf_mask3_round = 1430,
  CODE_FOR_avx512f_fnmadd_v8df_mask3 = 1431,
  CODE_FOR_avx512f_fnmadd_v8df_mask3_round = 1432,
#define CODE_FOR_fma_fnmsub_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fnmsub_v16sf_maskz_1 = 1441,
  CODE_FOR_fma_fnmsub_v16sf_maskz_1_round = 1442,
  CODE_FOR_fma_fnmsub_v8df_maskz_1 = 1445,
  CODE_FOR_fma_fnmsub_v8df_maskz_1_round = 1446,
  CODE_FOR_avx512f_fnmsub_v16sf_mask = 1447,
  CODE_FOR_avx512f_fnmsub_v16sf_mask_round = 1448,
  CODE_FOR_avx512f_fnmsub_v8df_mask = 1449,
  CODE_FOR_avx512f_fnmsub_v8df_mask_round = 1450,
  CODE_FOR_avx512f_fnmsub_v16sf_mask3 = 1451,
  CODE_FOR_avx512f_fnmsub_v16sf_mask3_round = 1452,
  CODE_FOR_avx512f_fnmsub_v8df_mask3 = 1453,
  CODE_FOR_avx512f_fnmsub_v8df_mask3_round = 1454,
#define CODE_FOR_fma_fmaddsub_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v2df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmaddsub_v16sf_maskz_1 = 1461,
  CODE_FOR_fma_fmaddsub_v16sf_maskz_1_round = 1462,
  CODE_FOR_fma_fmaddsub_v8df_maskz_1 = 1465,
  CODE_FOR_fma_fmaddsub_v8df_maskz_1_round = 1466,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask = 1467,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask_round = 1468,
  CODE_FOR_avx512f_fmaddsub_v8df_mask = 1469,
  CODE_FOR_avx512f_fmaddsub_v8df_mask_round = 1470,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask3 = 1471,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round = 1472,
  CODE_FOR_avx512f_fmaddsub_v8df_mask3 = 1473,
  CODE_FOR_avx512f_fmaddsub_v8df_mask3_round = 1474,
#define CODE_FOR_fma_fmsubadd_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v2df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmsubadd_v16sf_maskz_1 = 1481,
  CODE_FOR_fma_fmsubadd_v16sf_maskz_1_round = 1482,
  CODE_FOR_fma_fmsubadd_v8df_maskz_1 = 1485,
  CODE_FOR_fma_fmsubadd_v8df_maskz_1_round = 1486,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask = 1487,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask_round = 1488,
  CODE_FOR_avx512f_fmsubadd_v8df_mask = 1489,
  CODE_FOR_avx512f_fmsubadd_v8df_mask_round = 1490,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask3 = 1491,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round = 1492,
  CODE_FOR_avx512f_fmsubadd_v8df_mask3 = 1493,
  CODE_FOR_avx512f_fmsubadd_v8df_mask3_round = 1494,
  CODE_FOR_sse_cvtpi2ps = 1519,
  CODE_FOR_sse_cvtps2pi = 1520,
  CODE_FOR_sse_cvttps2pi = 1521,
  CODE_FOR_sse_cvtsi2ss = 1522,
  CODE_FOR_sse_cvtsi2ss_round = 1523,
#define CODE_FOR_sse_cvtsi2ssq CODE_FOR_nothing
#define CODE_FOR_sse_cvtsi2ssq_round CODE_FOR_nothing
  CODE_FOR_sse_cvtss2si = 1524,
  CODE_FOR_sse_cvtss2si_round = 1525,
  CODE_FOR_sse_cvtss2si_2 = 1526,
#define CODE_FOR_sse_cvtss2siq CODE_FOR_nothing
#define CODE_FOR_sse_cvtss2siq_round CODE_FOR_nothing
#define CODE_FOR_sse_cvtss2siq_2 CODE_FOR_nothing
  CODE_FOR_sse_cvttss2si = 1527,
  CODE_FOR_sse_cvttss2si_round = 1528,
#define CODE_FOR_sse_cvttss2siq CODE_FOR_nothing
#define CODE_FOR_sse_cvttss2siq_round CODE_FOR_nothing
  CODE_FOR_cvtusi2ss32 = 1529,
  CODE_FOR_cvtusi2ss32_round = 1530,
  CODE_FOR_cvtusi2sd32 = 1531,
#define CODE_FOR_cvtusi2sd32_round CODE_FOR_nothing
#define CODE_FOR_cvtusi2ss64 CODE_FOR_nothing
#define CODE_FOR_cvtusi2ss64_round CODE_FOR_nothing
#define CODE_FOR_cvtusi2sd64 CODE_FOR_nothing
#define CODE_FOR_cvtusi2sd64_round CODE_FOR_nothing
  CODE_FOR_floatv16siv16sf2 = 1532,
  CODE_FOR_floatv16siv16sf2_round = 1533,
  CODE_FOR_floatv16siv16sf2_mask = 1534,
  CODE_FOR_floatv16siv16sf2_mask_round = 1535,
  CODE_FOR_floatv8siv8sf2 = 1536,
#define CODE_FOR_floatv8siv8sf2_round CODE_FOR_nothing
#define CODE_FOR_floatv8siv8sf2_mask CODE_FOR_nothing
#define CODE_FOR_floatv8siv8sf2_mask_round CODE_FOR_nothing
  CODE_FOR_floatv4siv4sf2 = 1537,
#define CODE_FOR_floatv4siv4sf2_round CODE_FOR_nothing
#define CODE_FOR_floatv4siv4sf2_mask CODE_FOR_nothing
#define CODE_FOR_floatv4siv4sf2_mask_round CODE_FOR_nothing
  CODE_FOR_ufloatv16siv16sf2 = 1538,
  CODE_FOR_ufloatv16siv16sf2_round = 1539,
  CODE_FOR_ufloatv16siv16sf2_mask = 1540,
  CODE_FOR_ufloatv16siv16sf2_mask_round = 1541,
  CODE_FOR_avx_fix_notruncv8sfv8si = 1542,
  CODE_FOR_sse2_fix_notruncv4sfv4si = 1543,
  CODE_FOR_avx512f_fix_notruncv16sfv16si_mask = 1546,
  CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round = 1547,
  CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask = 1550,
  CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round = 1551,
  CODE_FOR_fix_truncv16sfv16si2 = 1552,
  CODE_FOR_fix_truncv16sfv16si2_round = 1553,
  CODE_FOR_fix_truncv16sfv16si2_mask = 1554,
  CODE_FOR_fix_truncv16sfv16si2_mask_round = 1555,
  CODE_FOR_ufix_truncv16sfv16si2 = 1556,
  CODE_FOR_ufix_truncv16sfv16si2_round = 1557,
  CODE_FOR_ufix_truncv16sfv16si2_mask = 1558,
  CODE_FOR_ufix_truncv16sfv16si2_mask_round = 1559,
  CODE_FOR_fix_truncv8sfv8si2 = 1560,
  CODE_FOR_fix_truncv4sfv4si2 = 1561,
  CODE_FOR_sse2_cvtpi2pd = 1562,
  CODE_FOR_sse2_cvtpd2pi = 1563,
  CODE_FOR_sse2_cvttpd2pi = 1564,
  CODE_FOR_sse2_cvtsi2sd = 1565,
#define CODE_FOR_sse2_cvtsi2sdq CODE_FOR_nothing
#define CODE_FOR_sse2_cvtsi2sdq_round CODE_FOR_nothing
  CODE_FOR_avx512f_vcvtss2usi = 1566,
  CODE_FOR_avx512f_vcvtss2usi_round = 1567,
#define CODE_FOR_avx512f_vcvtss2usiq CODE_FOR_nothing
#define CODE_FOR_avx512f_vcvtss2usiq_round CODE_FOR_nothing
  CODE_FOR_avx512f_vcvttss2usi = 1568,
  CODE_FOR_avx512f_vcvttss2usi_round = 1569,
#define CODE_FOR_avx512f_vcvttss2usiq CODE_FOR_nothing
#define CODE_FOR_avx512f_vcvttss2usiq_round CODE_FOR_nothing
  CODE_FOR_avx512f_vcvtsd2usi = 1570,
  CODE_FOR_avx512f_vcvtsd2usi_round = 1571,
#define CODE_FOR_avx512f_vcvtsd2usiq CODE_FOR_nothing
#define CODE_FOR_avx512f_vcvtsd2usiq_round CODE_FOR_nothing
  CODE_FOR_avx512f_vcvttsd2usi = 1572,
  CODE_FOR_avx512f_vcvttsd2usi_round = 1573,
#define CODE_FOR_avx512f_vcvttsd2usiq CODE_FOR_nothing
#define CODE_FOR_avx512f_vcvttsd2usiq_round CODE_FOR_nothing
  CODE_FOR_sse2_cvtsd2si = 1574,
  CODE_FOR_sse2_cvtsd2si_round = 1575,
  CODE_FOR_sse2_cvtsd2si_2 = 1576,
#define CODE_FOR_sse2_cvtsd2siq CODE_FOR_nothing
#define CODE_FOR_sse2_cvtsd2siq_round CODE_FOR_nothing
#define CODE_FOR_sse2_cvtsd2siq_2 CODE_FOR_nothing
  CODE_FOR_sse2_cvttsd2si = 1577,
  CODE_FOR_sse2_cvttsd2si_round = 1578,
#define CODE_FOR_sse2_cvttsd2siq CODE_FOR_nothing
#define CODE_FOR_sse2_cvttsd2siq_round CODE_FOR_nothing
  CODE_FOR_floatv8siv8df2 = 1579,
  CODE_FOR_floatv8siv8df2_mask = 1580,
  CODE_FOR_floatv4siv4df2 = 1581,
#define CODE_FOR_floatv4siv4df2_mask CODE_FOR_nothing
  CODE_FOR_ufloatv8siv8df = 1582,
  CODE_FOR_ufloatv8siv8df_mask = 1583,
  CODE_FOR_avx512f_cvtdq2pd512_2 = 1584,
  CODE_FOR_avx_cvtdq2pd256_2 = 1585,
  CODE_FOR_sse2_cvtdq2pd = 1586,
  CODE_FOR_avx512f_cvtpd2dq512_mask = 1589,
  CODE_FOR_avx512f_cvtpd2dq512_mask_round = 1590,
  CODE_FOR_avx_cvtpd2dq256 = 1591,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si = 1594,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si_round = 1595,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask = 1596,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round = 1597,
  CODE_FOR_fix_truncv8dfv8si2 = 1598,
  CODE_FOR_fix_truncv8dfv8si2_round = 1599,
  CODE_FOR_fix_truncv8dfv8si2_mask = 1600,
  CODE_FOR_fix_truncv8dfv8si2_mask_round = 1601,
  CODE_FOR_ufix_truncv8dfv8si2 = 1602,
  CODE_FOR_ufix_truncv8dfv8si2_round = 1603,
  CODE_FOR_ufix_truncv8dfv8si2_mask = 1604,
  CODE_FOR_ufix_truncv8dfv8si2_mask_round = 1605,
  CODE_FOR_fix_truncv4dfv4si2 = 1606,
  CODE_FOR_sse2_cvtsd2ss = 1609,
  CODE_FOR_sse2_cvtsd2ss_round = 1610,
  CODE_FOR_sse2_cvtss2sd = 1611,
  CODE_FOR_sse2_cvtss2sd_round = 1612,
  CODE_FOR_avx512f_cvtpd2ps512_mask = 1615,
  CODE_FOR_avx512f_cvtpd2ps512_mask_round = 1616,
  CODE_FOR_avx_cvtpd2ps256 = 1617,
  CODE_FOR_avx512f_cvtps2pd512 = 1619,
  CODE_FOR_avx512f_cvtps2pd512_round = 1620,
  CODE_FOR_avx512f_cvtps2pd512_mask = 1621,
  CODE_FOR_avx512f_cvtps2pd512_mask_round = 1622,
  CODE_FOR_avx_cvtps2pd256 = 1623,
#define CODE_FOR_avx_cvtps2pd256_round CODE_FOR_nothing
#define CODE_FOR_avx_cvtps2pd256_mask CODE_FOR_nothing
#define CODE_FOR_avx_cvtps2pd256_mask_round CODE_FOR_nothing
  CODE_FOR_vec_unpacks_lo_v16sf = 1625,
  CODE_FOR_sse2_cvtps2pd = 1626,
  CODE_FOR_sse_movhlps = 1627,
  CODE_FOR_sse_movlhps = 1628,
  CODE_FOR_avx512f_unpckhps512_mask = 1630,
  CODE_FOR_avx_unpckhps256 = 1631,
  CODE_FOR_vec_interleave_highv4sf = 1632,
  CODE_FOR_avx512f_unpcklps512_mask = 1634,
  CODE_FOR_avx_unpcklps256 = 1635,
  CODE_FOR_vec_interleave_lowv4sf = 1636,
  CODE_FOR_avx_movshdup256 = 1637,
  CODE_FOR_sse3_movshdup = 1638,
  CODE_FOR_avx512f_movshdup512_mask = 1640,
  CODE_FOR_avx_movsldup256 = 1641,
  CODE_FOR_sse3_movsldup = 1642,
  CODE_FOR_avx512f_movsldup512_mask = 1644,
  CODE_FOR_avx_shufps256_1 = 1645,
  CODE_FOR_sse_shufps_v4si = 1646,
  CODE_FOR_sse_shufps_v4sf = 1647,
  CODE_FOR_sse_storehps = 1648,
  CODE_FOR_sse_loadhps = 1649,
  CODE_FOR_sse_storelps = 1650,
  CODE_FOR_sse_loadlps = 1651,
  CODE_FOR_sse_movss = 1652,
  CODE_FOR_avx2_vec_dupv8sf = 1653,
  CODE_FOR_avx2_vec_dupv4sf = 1654,
  CODE_FOR_avx2_vec_dupv8sf_1 = 1655,
  CODE_FOR_vec_dupv4sf = 1656,
  CODE_FOR_vec_setv4si_0 = 1660,
  CODE_FOR_vec_setv4sf_0 = 1661,
  CODE_FOR_sse4_1_insertps = 1663,
  CODE_FOR_avx512f_vextractf32x4_1_maskm = 1667,
  CODE_FOR_avx512f_vextracti32x4_1_maskm = 1668,
  CODE_FOR_avx512f_vextractf32x4_1_mask = 1670,
  CODE_FOR_avx512f_vextracti32x4_1_mask = 1672,
  CODE_FOR_vec_extract_lo_v8df_maskm = 1673,
  CODE_FOR_vec_extract_lo_v8di_maskm = 1674,
  CODE_FOR_vec_extract_lo_v8df = 1675,
  CODE_FOR_vec_extract_lo_v8df_mask = 1676,
  CODE_FOR_vec_extract_lo_v8di = 1677,
  CODE_FOR_vec_extract_lo_v8di_mask = 1678,
  CODE_FOR_vec_extract_hi_v8df_maskm = 1679,
  CODE_FOR_vec_extract_hi_v8di_maskm = 1680,
  CODE_FOR_vec_extract_hi_v8df = 1681,
  CODE_FOR_vec_extract_hi_v8df_mask = 1682,
  CODE_FOR_vec_extract_hi_v8di = 1683,
  CODE_FOR_vec_extract_hi_v8di_mask = 1684,
  CODE_FOR_vec_extract_lo_v16sf = 1685,
  CODE_FOR_vec_extract_lo_v16si = 1686,
  CODE_FOR_vec_extract_hi_v16sf = 1687,
  CODE_FOR_vec_extract_hi_v16si = 1688,
  CODE_FOR_vec_extract_lo_v4di = 1689,
  CODE_FOR_vec_extract_lo_v4df = 1690,
  CODE_FOR_vec_extract_hi_v4di = 1691,
  CODE_FOR_vec_extract_hi_v4df = 1692,
  CODE_FOR_vec_extract_lo_v8si = 1693,
  CODE_FOR_vec_extract_lo_v8sf = 1694,
  CODE_FOR_vec_extract_hi_v8si = 1695,
  CODE_FOR_vec_extract_hi_v8sf = 1696,
  CODE_FOR_vec_extract_lo_v32hi = 1697,
  CODE_FOR_vec_extract_hi_v32hi = 1698,
  CODE_FOR_vec_extract_lo_v16hi = 1699,
  CODE_FOR_vec_extract_hi_v16hi = 1700,
  CODE_FOR_vec_extract_lo_v64qi = 1701,
  CODE_FOR_vec_extract_hi_v64qi = 1702,
  CODE_FOR_vec_extract_lo_v32qi = 1703,
  CODE_FOR_vec_extract_hi_v32qi = 1704,
  CODE_FOR_avx512f_unpckhpd512_mask = 1706,
  CODE_FOR_avx_unpckhpd256 = 1707,
  CODE_FOR_avx512f_vmscalefv4sf = 1713,
  CODE_FOR_avx512f_vmscalefv4sf_round = 1714,
  CODE_FOR_avx512f_vmscalefv2df = 1715,
  CODE_FOR_avx512f_vmscalefv2df_round = 1716,
  CODE_FOR_avx512f_scalefv16sf = 1717,
  CODE_FOR_avx512f_scalefv16sf_round = 1718,
  CODE_FOR_avx512f_scalefv16sf_mask = 1719,
  CODE_FOR_avx512f_scalefv16sf_mask_round = 1720,
  CODE_FOR_avx512f_scalefv8df = 1721,
  CODE_FOR_avx512f_scalefv8df_round = 1722,
  CODE_FOR_avx512f_scalefv8df_mask = 1723,
  CODE_FOR_avx512f_scalefv8df_mask_round = 1724,
  CODE_FOR_avx512f_vternlogv16si = 1725,
  CODE_FOR_avx512f_vternlogv16si_maskz_1 = 1726,
  CODE_FOR_avx512f_vternlogv8di = 1727,
  CODE_FOR_avx512f_vternlogv8di_maskz_1 = 1728,
  CODE_FOR_avx512f_vternlogv16si_mask = 1729,
  CODE_FOR_avx512f_vternlogv8di_mask = 1730,
  CODE_FOR_avx512f_getexpv16sf = 1731,
  CODE_FOR_avx512f_getexpv16sf_round = 1732,
  CODE_FOR_avx512f_getexpv16sf_mask = 1733,
  CODE_FOR_avx512f_getexpv16sf_mask_round = 1734,
  CODE_FOR_avx512f_getexpv8df = 1735,
  CODE_FOR_avx512f_getexpv8df_round = 1736,
  CODE_FOR_avx512f_getexpv8df_mask = 1737,
  CODE_FOR_avx512f_getexpv8df_mask_round = 1738,
  CODE_FOR_avx512f_sgetexpv4sf = 1739,
  CODE_FOR_avx512f_sgetexpv4sf_round = 1740,
  CODE_FOR_avx512f_sgetexpv2df = 1741,
  CODE_FOR_avx512f_sgetexpv2df_round = 1742,
  CODE_FOR_avx512f_alignv16si_mask = 1744,
  CODE_FOR_avx512f_alignv8di_mask = 1746,
  CODE_FOR_avx512f_fixupimmv16sf = 1747,
  CODE_FOR_avx512f_fixupimmv16sf_round = 1748,
  CODE_FOR_avx512f_fixupimmv16sf_maskz_1 = 1749,
  CODE_FOR_avx512f_fixupimmv16sf_maskz_1_round = 1750,
  CODE_FOR_avx512f_fixupimmv8df = 1751,
  CODE_FOR_avx512f_fixupimmv8df_round = 1752,
  CODE_FOR_avx512f_fixupimmv8df_maskz_1 = 1753,
  CODE_FOR_avx512f_fixupimmv8df_maskz_1_round = 1754,
  CODE_FOR_avx512f_fixupimmv16sf_mask = 1755,
  CODE_FOR_avx512f_fixupimmv16sf_mask_round = 1756,
  CODE_FOR_avx512f_fixupimmv8df_mask = 1757,
  CODE_FOR_avx512f_fixupimmv8df_mask_round = 1758,
  CODE_FOR_avx512f_sfixupimmv4sf = 1759,
  CODE_FOR_avx512f_sfixupimmv4sf_round = 1760,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz_1 = 1761,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz_1_round = 1762,
  CODE_FOR_avx512f_sfixupimmv2df = 1763,
  CODE_FOR_avx512f_sfixupimmv2df_round = 1764,
  CODE_FOR_avx512f_sfixupimmv2df_maskz_1 = 1765,
  CODE_FOR_avx512f_sfixupimmv2df_maskz_1_round = 1766,
  CODE_FOR_avx512f_sfixupimmv4sf_mask = 1767,
  CODE_FOR_avx512f_sfixupimmv4sf_mask_round = 1768,
  CODE_FOR_avx512f_sfixupimmv2df_mask = 1769,
  CODE_FOR_avx512f_sfixupimmv2df_mask_round = 1770,
  CODE_FOR_avx512f_rndscalev16sf = 1771,
  CODE_FOR_avx512f_rndscalev16sf_round = 1772,
  CODE_FOR_avx512f_rndscalev16sf_mask = 1773,
  CODE_FOR_avx512f_rndscalev16sf_mask_round = 1774,
  CODE_FOR_avx512f_rndscalev8df = 1775,
  CODE_FOR_avx512f_rndscalev8df_round = 1776,
  CODE_FOR_avx512f_rndscalev8df_mask = 1777,
  CODE_FOR_avx512f_rndscalev8df_mask_round = 1778,
  CODE_FOR_avx512f_rndscalev4sf = 1779,
  CODE_FOR_avx512f_rndscalev4sf_round = 1780,
  CODE_FOR_avx512f_rndscalev2df = 1781,
  CODE_FOR_avx512f_rndscalev2df_round = 1782,
  CODE_FOR_avx512f_shufps512_1 = 1783,
  CODE_FOR_avx512f_shufps512_1_mask = 1784,
  CODE_FOR_avx512f_shufpd512_1 = 1785,
  CODE_FOR_avx512f_shufpd512_1_mask = 1786,
  CODE_FOR_avx_shufpd256_1 = 1787,
  CODE_FOR_avx2_interleave_highv4di = 1788,
  CODE_FOR_avx512f_interleave_highv8di_mask = 1790,
  CODE_FOR_vec_interleave_highv2di = 1791,
  CODE_FOR_avx2_interleave_lowv4di = 1792,
  CODE_FOR_avx512f_interleave_lowv8di_mask = 1794,
  CODE_FOR_vec_interleave_lowv2di = 1795,
  CODE_FOR_sse2_shufpd_v2di = 1796,
  CODE_FOR_sse2_shufpd_v2df = 1797,
  CODE_FOR_sse2_storehpd = 1798,
  CODE_FOR_sse2_storelpd = 1800,
  CODE_FOR_sse2_loadhpd = 1802,
  CODE_FOR_sse2_loadlpd = 1803,
  CODE_FOR_sse2_movsd = 1804,
  CODE_FOR_vec_dupv2df = 1805,
  CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask = 1819,
  CODE_FOR_avx512f_truncatev16siv16qi2_mask = 1820,
  CODE_FOR_avx512f_us_truncatev16siv16qi2_mask = 1821,
  CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask = 1822,
  CODE_FOR_avx512f_truncatev16siv16hi2_mask = 1823,
  CODE_FOR_avx512f_us_truncatev16siv16hi2_mask = 1824,
  CODE_FOR_avx512f_ss_truncatev8div8si2_mask = 1825,
  CODE_FOR_avx512f_truncatev8div8si2_mask = 1826,
  CODE_FOR_avx512f_us_truncatev8div8si2_mask = 1827,
  CODE_FOR_avx512f_ss_truncatev8div8hi2_mask = 1828,
  CODE_FOR_avx512f_truncatev8div8hi2_mask = 1829,
  CODE_FOR_avx512f_us_truncatev8div8hi2_mask = 1830,
  CODE_FOR_avx512f_ss_truncatev8div16qi2_mask = 1837,
  CODE_FOR_avx512f_truncatev8div16qi2_mask = 1838,
  CODE_FOR_avx512f_us_truncatev8div16qi2_mask = 1839,
  CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store = 1840,
  CODE_FOR_avx512f_truncatev8div16qi2_mask_store = 1841,
  CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store = 1842,
  CODE_FOR_ashrv16hi3 = 1919,
  CODE_FOR_ashrv8hi3 = 1920,
  CODE_FOR_ashrv8si3 = 1921,
  CODE_FOR_ashrv4si3 = 1922,
  CODE_FOR_ashrv16si3 = 1923,
  CODE_FOR_ashrv16si3_mask = 1924,
  CODE_FOR_ashrv8di3 = 1925,
  CODE_FOR_ashrv8di3_mask = 1926,
  CODE_FOR_ashlv16hi3 = 1927,
  CODE_FOR_lshrv16hi3 = 1928,
  CODE_FOR_ashlv8hi3 = 1929,
  CODE_FOR_lshrv8hi3 = 1930,
  CODE_FOR_ashlv8si3 = 1931,
  CODE_FOR_lshrv8si3 = 1932,
  CODE_FOR_ashlv4si3 = 1933,
  CODE_FOR_lshrv4si3 = 1934,
  CODE_FOR_ashlv4di3 = 1935,
  CODE_FOR_lshrv4di3 = 1936,
  CODE_FOR_ashlv2di3 = 1937,
  CODE_FOR_lshrv2di3 = 1938,
  CODE_FOR_ashlv16si3 = 1939,
  CODE_FOR_ashlv16si3_mask = 1940,
  CODE_FOR_lshrv16si3 = 1941,
  CODE_FOR_lshrv16si3_mask = 1942,
  CODE_FOR_ashlv8di3 = 1943,
  CODE_FOR_ashlv8di3_mask = 1944,
  CODE_FOR_lshrv8di3 = 1945,
  CODE_FOR_lshrv8di3_mask = 1946,
  CODE_FOR_avx2_ashlv2ti3 = 1947,
  CODE_FOR_sse2_ashlv1ti3 = 1948,
  CODE_FOR_avx2_lshrv2ti3 = 1949,
  CODE_FOR_sse2_lshrv1ti3 = 1950,
  CODE_FOR_avx512f_rolvv16si = 1951,
  CODE_FOR_avx512f_rolvv16si_mask = 1952,
  CODE_FOR_avx512f_rorvv16si = 1953,
  CODE_FOR_avx512f_rorvv16si_mask = 1954,
  CODE_FOR_avx512f_rolvv8di = 1955,
  CODE_FOR_avx512f_rolvv8di_mask = 1956,
  CODE_FOR_avx512f_rorvv8di = 1957,
  CODE_FOR_avx512f_rorvv8di_mask = 1958,
  CODE_FOR_avx512f_rolv16si = 1959,
  CODE_FOR_avx512f_rolv16si_mask = 1960,
  CODE_FOR_avx512f_rorv16si = 1961,
  CODE_FOR_avx512f_rorv16si_mask = 1962,
  CODE_FOR_avx512f_rolv8di = 1963,
  CODE_FOR_avx512f_rolv8di_mask = 1964,
  CODE_FOR_avx512f_rorv8di = 1965,
  CODE_FOR_avx512f_rorv8di_mask = 1966,
  CODE_FOR_avx512f_eqv16si3_1 = 2051,
  CODE_FOR_avx512f_eqv16si3_mask_1 = 2052,
  CODE_FOR_avx512f_eqv8di3_1 = 2053,
  CODE_FOR_avx512f_eqv8di3_mask_1 = 2054,
  CODE_FOR_sse4_2_gtv2di3 = 2059,
  CODE_FOR_avx2_gtv32qi3 = 2060,
  CODE_FOR_avx2_gtv16hi3 = 2061,
  CODE_FOR_avx2_gtv8si3 = 2062,
  CODE_FOR_avx2_gtv4di3 = 2063,
  CODE_FOR_avx512f_gtv16si3 = 2064,
  CODE_FOR_avx512f_gtv16si3_mask = 2065,
  CODE_FOR_avx512f_gtv8di3 = 2066,
  CODE_FOR_avx512f_gtv8di3_mask = 2067,
  CODE_FOR_sse2_gtv16qi3 = 2068,
  CODE_FOR_sse2_gtv8hi3 = 2069,
  CODE_FOR_sse2_gtv4si3 = 2070,
  CODE_FOR_andv16si3_mask = 2084,
  CODE_FOR_iorv16si3_mask = 2086,
  CODE_FOR_xorv16si3_mask = 2088,
  CODE_FOR_andv8di3_mask = 2090,
  CODE_FOR_iorv8di3_mask = 2092,
  CODE_FOR_xorv8di3_mask = 2094,
#define CODE_FOR_andv16qi3_mask CODE_FOR_nothing
#define CODE_FOR_iorv16qi3_mask CODE_FOR_nothing
#define CODE_FOR_xorv16qi3_mask CODE_FOR_nothing
#define CODE_FOR_andv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_iorv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_xorv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_andv8hi3_mask CODE_FOR_nothing
#define CODE_FOR_iorv8hi3_mask CODE_FOR_nothing
#define CODE_FOR_xorv8hi3_mask CODE_FOR_nothing
#define CODE_FOR_andv8si3_mask CODE_FOR_nothing
#define CODE_FOR_iorv8si3_mask CODE_FOR_nothing
#define CODE_FOR_xorv8si3_mask CODE_FOR_nothing
#define CODE_FOR_andv4si3_mask CODE_FOR_nothing
#define CODE_FOR_iorv4si3_mask CODE_FOR_nothing
#define CODE_FOR_xorv4si3_mask CODE_FOR_nothing
#define CODE_FOR_andv4di3_mask CODE_FOR_nothing
#define CODE_FOR_iorv4di3_mask CODE_FOR_nothing
#define CODE_FOR_xorv4di3_mask CODE_FOR_nothing
#define CODE_FOR_andv2di3_mask CODE_FOR_nothing
#define CODE_FOR_iorv2di3_mask CODE_FOR_nothing
#define CODE_FOR_xorv2di3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_testmv16si3 = 2119,
  CODE_FOR_avx512f_testmv16si3_mask = 2120,
  CODE_FOR_avx512f_testmv8di3 = 2121,
  CODE_FOR_avx512f_testmv8di3_mask = 2122,
  CODE_FOR_avx512f_testnmv16si3 = 2123,
  CODE_FOR_avx512f_testnmv16si3_mask = 2124,
  CODE_FOR_avx512f_testnmv8di3 = 2125,
  CODE_FOR_avx512f_testnmv8di3_mask = 2126,
  CODE_FOR_avx2_packsswb = 2127,
  CODE_FOR_sse2_packsswb = 2128,
  CODE_FOR_avx2_packssdw = 2129,
  CODE_FOR_sse2_packssdw = 2130,
  CODE_FOR_avx2_packuswb = 2131,
  CODE_FOR_sse2_packuswb = 2132,
  CODE_FOR_avx2_interleave_highv32qi = 2133,
  CODE_FOR_vec_interleave_highv16qi = 2134,
  CODE_FOR_avx2_interleave_lowv32qi = 2135,
  CODE_FOR_vec_interleave_lowv16qi = 2136,
  CODE_FOR_avx2_interleave_highv16hi = 2137,
  CODE_FOR_vec_interleave_highv8hi = 2138,
  CODE_FOR_avx2_interleave_lowv16hi = 2139,
  CODE_FOR_vec_interleave_lowv8hi = 2140,
  CODE_FOR_avx2_interleave_highv8si = 2141,
  CODE_FOR_avx512f_interleave_highv16si_mask = 2143,
  CODE_FOR_vec_interleave_highv4si = 2144,
  CODE_FOR_avx2_interleave_lowv8si = 2145,
  CODE_FOR_avx512f_interleave_lowv16si_mask = 2147,
  CODE_FOR_vec_interleave_lowv4si = 2148,
  CODE_FOR_sse4_1_pinsrb = 2149,
  CODE_FOR_sse2_pinsrw = 2150,
  CODE_FOR_sse4_1_pinsrd = 2151,
  CODE_FOR_sse4_1_pinsrq = 2152,
  CODE_FOR_avx512f_vinsertf32x4_1_mask = 2154,
  CODE_FOR_avx512f_vinserti32x4_1_mask = 2156,
  CODE_FOR_vec_set_lo_v8df = 2157,
  CODE_FOR_vec_set_lo_v8df_mask = 2158,
  CODE_FOR_vec_set_lo_v8di = 2159,
  CODE_FOR_vec_set_lo_v8di_mask = 2160,
  CODE_FOR_vec_set_hi_v8df = 2161,
  CODE_FOR_vec_set_hi_v8df_mask = 2162,
  CODE_FOR_vec_set_hi_v8di = 2163,
  CODE_FOR_vec_set_hi_v8di_mask = 2164,
  CODE_FOR_avx512f_shuf_f64x2_1 = 2165,
  CODE_FOR_avx512f_shuf_f64x2_1_mask = 2166,
  CODE_FOR_avx512f_shuf_i64x2_1 = 2167,
  CODE_FOR_avx512f_shuf_i64x2_1_mask = 2168,
  CODE_FOR_avx512f_shuf_f32x4_1 = 2169,
  CODE_FOR_avx512f_shuf_f32x4_1_mask = 2170,
  CODE_FOR_avx512f_shuf_i32x4_1 = 2171,
  CODE_FOR_avx512f_shuf_i32x4_1_mask = 2172,
  CODE_FOR_avx512f_pshufd_1 = 2173,
  CODE_FOR_avx512f_pshufd_1_mask = 2174,
  CODE_FOR_avx2_pshufd_1 = 2175,
  CODE_FOR_sse2_pshufd_1 = 2176,
  CODE_FOR_avx2_pshuflw_1 = 2177,
  CODE_FOR_sse2_pshuflw_1 = 2178,
  CODE_FOR_avx2_pshufhw_1 = 2179,
  CODE_FOR_sse2_pshufhw_1 = 2180,
  CODE_FOR_sse2_loadld = 2181,
  CODE_FOR_vec_concatv2di = 2199,
  CODE_FOR_avx2_psadbw = 2204,
  CODE_FOR_sse2_psadbw = 2205,
  CODE_FOR_avx_movmskps256 = 2206,
  CODE_FOR_sse_movmskps = 2207,
  CODE_FOR_avx_movmskpd256 = 2208,
  CODE_FOR_sse2_movmskpd = 2209,
  CODE_FOR_avx2_pmovmskb = 2210,
  CODE_FOR_sse2_pmovmskb = 2211,
  CODE_FOR_sse_ldmxcsr = 2214,
  CODE_FOR_sse_stmxcsr = 2215,
  CODE_FOR_sse2_clflush = 2216,
  CODE_FOR_sse3_mwait = 2217,
  CODE_FOR_sse3_monitor_si = 2218,
  CODE_FOR_sse3_monitor_di = 2219,
  CODE_FOR_avx2_phaddwv16hi3 = 2220,
  CODE_FOR_avx2_phaddswv16hi3 = 2221,
  CODE_FOR_avx2_phsubwv16hi3 = 2222,
  CODE_FOR_avx2_phsubswv16hi3 = 2223,
  CODE_FOR_ssse3_phaddwv8hi3 = 2224,
  CODE_FOR_ssse3_phaddswv8hi3 = 2225,
  CODE_FOR_ssse3_phsubwv8hi3 = 2226,
  CODE_FOR_ssse3_phsubswv8hi3 = 2227,
  CODE_FOR_ssse3_phaddwv4hi3 = 2228,
  CODE_FOR_ssse3_phaddswv4hi3 = 2229,
  CODE_FOR_ssse3_phsubwv4hi3 = 2230,
  CODE_FOR_ssse3_phsubswv4hi3 = 2231,
  CODE_FOR_avx2_phadddv8si3 = 2232,
  CODE_FOR_avx2_phsubdv8si3 = 2233,
  CODE_FOR_ssse3_phadddv4si3 = 2234,
  CODE_FOR_ssse3_phsubdv4si3 = 2235,
  CODE_FOR_ssse3_phadddv2si3 = 2236,
  CODE_FOR_ssse3_phsubdv2si3 = 2237,
  CODE_FOR_avx2_pmaddubsw256 = 2238,
  CODE_FOR_ssse3_pmaddubsw128 = 2239,
  CODE_FOR_ssse3_pmaddubsw = 2240,
  CODE_FOR_avx2_pshufbv32qi3 = 2244,
  CODE_FOR_ssse3_pshufbv16qi3 = 2245,
  CODE_FOR_ssse3_pshufbv8qi3 = 2246,
  CODE_FOR_avx2_psignv32qi3 = 2247,
  CODE_FOR_ssse3_psignv16qi3 = 2248,
  CODE_FOR_avx2_psignv16hi3 = 2249,
  CODE_FOR_ssse3_psignv8hi3 = 2250,
  CODE_FOR_avx2_psignv8si3 = 2251,
  CODE_FOR_ssse3_psignv4si3 = 2252,
  CODE_FOR_ssse3_psignv8qi3 = 2253,
  CODE_FOR_ssse3_psignv4hi3 = 2254,
  CODE_FOR_ssse3_psignv2si3 = 2255,
  CODE_FOR_avx2_palignrv2ti = 2256,
  CODE_FOR_ssse3_palignrti = 2257,
  CODE_FOR_ssse3_palignrdi = 2258,
#define CODE_FOR_absv16qi2_mask CODE_FOR_nothing
#define CODE_FOR_absv16hi2_mask CODE_FOR_nothing
#define CODE_FOR_absv8hi2_mask CODE_FOR_nothing
  CODE_FOR_absv16si2_mask = 2264,
#define CODE_FOR_absv8si2_mask CODE_FOR_nothing
#define CODE_FOR_absv4si2_mask CODE_FOR_nothing
  CODE_FOR_absv8di2_mask = 2268,
  CODE_FOR_absv8qi2 = 2269,
  CODE_FOR_absv4hi2 = 2270,
  CODE_FOR_absv2si2 = 2271,
  CODE_FOR_sse4a_movntsf = 2272,
  CODE_FOR_sse4a_movntdf = 2273,
  CODE_FOR_sse4a_vmmovntv4sf = 2274,
  CODE_FOR_sse4a_vmmovntv2df = 2275,
  CODE_FOR_sse4a_extrqi = 2276,
  CODE_FOR_sse4a_extrq = 2277,
  CODE_FOR_sse4a_insertqi = 2278,
  CODE_FOR_sse4a_insertq = 2279,
  CODE_FOR_avx_blendps256 = 2280,
  CODE_FOR_sse4_1_blendps = 2281,
  CODE_FOR_avx_blendpd256 = 2282,
  CODE_FOR_sse4_1_blendpd = 2283,
  CODE_FOR_avx_blendvps256 = 2284,
  CODE_FOR_sse4_1_blendvps = 2285,
  CODE_FOR_avx_blendvpd256 = 2286,
  CODE_FOR_sse4_1_blendvpd = 2287,
  CODE_FOR_avx_dpps256 = 2288,
  CODE_FOR_sse4_1_dpps = 2289,
  CODE_FOR_avx_dppd256 = 2290,
  CODE_FOR_sse4_1_dppd = 2291,
  CODE_FOR_avx512f_movntdqa = 2292,
  CODE_FOR_avx2_movntdqa = 2293,
  CODE_FOR_sse4_1_movntdqa = 2294,
  CODE_FOR_avx2_mpsadbw = 2295,
  CODE_FOR_sse4_1_mpsadbw = 2296,
  CODE_FOR_avx2_packusdw = 2297,
  CODE_FOR_sse4_1_packusdw = 2298,
  CODE_FOR_avx2_pblendvb = 2299,
  CODE_FOR_sse4_1_pblendvb = 2300,
  CODE_FOR_sse4_1_pblendw = 2301,
  CODE_FOR_avx2_pblenddv8si = 2303,
  CODE_FOR_avx2_pblenddv4si = 2304,
  CODE_FOR_sse4_1_phminposuw = 2305,
  CODE_FOR_avx2_sign_extendv16qiv16hi2 = 2306,
  CODE_FOR_avx2_zero_extendv16qiv16hi2 = 2307,
  CODE_FOR_sse4_1_sign_extendv8qiv8hi2 = 2308,
  CODE_FOR_sse4_1_zero_extendv8qiv8hi2 = 2309,
  CODE_FOR_avx512f_sign_extendv16qiv16si2_mask = 2311,
  CODE_FOR_avx512f_zero_extendv16qiv16si2_mask = 2313,
  CODE_FOR_avx2_sign_extendv8qiv8si2 = 2314,
  CODE_FOR_avx2_zero_extendv8qiv8si2 = 2315,
  CODE_FOR_sse4_1_sign_extendv4qiv4si2 = 2316,
  CODE_FOR_sse4_1_zero_extendv4qiv4si2 = 2317,
  CODE_FOR_avx512f_sign_extendv16hiv16si2 = 2318,
  CODE_FOR_avx512f_sign_extendv16hiv16si2_mask = 2319,
  CODE_FOR_avx512f_zero_extendv16hiv16si2 = 2320,
  CODE_FOR_avx512f_zero_extendv16hiv16si2_mask = 2321,
  CODE_FOR_avx2_sign_extendv8hiv8si2 = 2322,
  CODE_FOR_avx2_zero_extendv8hiv8si2 = 2323,
  CODE_FOR_sse4_1_sign_extendv4hiv4si2 = 2324,
  CODE_FOR_sse4_1_zero_extendv4hiv4si2 = 2325,
  CODE_FOR_avx512f_sign_extendv8qiv8di2 = 2326,
  CODE_FOR_avx512f_sign_extendv8qiv8di2_mask = 2327,
  CODE_FOR_avx512f_zero_extendv8qiv8di2 = 2328,
  CODE_FOR_avx512f_zero_extendv8qiv8di2_mask = 2329,
  CODE_FOR_avx2_sign_extendv4qiv4di2 = 2330,
  CODE_FOR_avx2_zero_extendv4qiv4di2 = 2331,
  CODE_FOR_sse4_1_sign_extendv2qiv2di2 = 2332,
  CODE_FOR_sse4_1_zero_extendv2qiv2di2 = 2333,
  CODE_FOR_avx512f_sign_extendv8hiv8di2 = 2334,
  CODE_FOR_avx512f_sign_extendv8hiv8di2_mask = 2335,
  CODE_FOR_avx512f_zero_extendv8hiv8di2 = 2336,
  CODE_FOR_avx512f_zero_extendv8hiv8di2_mask = 2337,
  CODE_FOR_avx2_sign_extendv4hiv4di2 = 2338,
  CODE_FOR_avx2_zero_extendv4hiv4di2 = 2339,
  CODE_FOR_sse4_1_sign_extendv2hiv2di2 = 2340,
  CODE_FOR_sse4_1_zero_extendv2hiv2di2 = 2341,
  CODE_FOR_avx512f_sign_extendv8siv8di2 = 2342,
  CODE_FOR_avx512f_sign_extendv8siv8di2_mask = 2343,
  CODE_FOR_avx512f_zero_extendv8siv8di2 = 2344,
  CODE_FOR_avx512f_zero_extendv8siv8di2_mask = 2345,
  CODE_FOR_avx2_sign_extendv4siv4di2 = 2346,
  CODE_FOR_avx2_zero_extendv4siv4di2 = 2347,
  CODE_FOR_sse4_1_sign_extendv2siv2di2 = 2348,
  CODE_FOR_sse4_1_zero_extendv2siv2di2 = 2349,
  CODE_FOR_avx_vtestps256 = 2350,
  CODE_FOR_avx_vtestps = 2351,
  CODE_FOR_avx_vtestpd256 = 2352,
  CODE_FOR_avx_vtestpd = 2353,
  CODE_FOR_avx_ptest256 = 2354,
  CODE_FOR_sse4_1_ptest = 2355,
  CODE_FOR_avx_roundps256 = 2356,
  CODE_FOR_sse4_1_roundps = 2357,
  CODE_FOR_avx_roundpd256 = 2358,
  CODE_FOR_sse4_1_roundpd = 2359,
  CODE_FOR_sse4_1_roundss = 2360,
  CODE_FOR_sse4_1_roundsd = 2361,
  CODE_FOR_sse4_2_pcmpestr = 2362,
  CODE_FOR_sse4_2_pcmpestri = 2364,
  CODE_FOR_sse4_2_pcmpestrm = 2365,
  CODE_FOR_sse4_2_pcmpestr_cconly = 2366,
  CODE_FOR_sse4_2_pcmpistr = 2367,
  CODE_FOR_sse4_2_pcmpistri = 2369,
  CODE_FOR_sse4_2_pcmpistrm = 2370,
  CODE_FOR_sse4_2_pcmpistr_cconly = 2371,
  CODE_FOR_avx512er_exp2v16sf = 2404,
  CODE_FOR_avx512er_exp2v16sf_round = 2405,
  CODE_FOR_avx512er_exp2v16sf_mask = 2406,
  CODE_FOR_avx512er_exp2v16sf_mask_round = 2407,
  CODE_FOR_avx512er_exp2v8df = 2408,
  CODE_FOR_avx512er_exp2v8df_round = 2409,
  CODE_FOR_avx512er_exp2v8df_mask = 2410,
  CODE_FOR_avx512er_exp2v8df_mask_round = 2411,
  CODE_FOR_avx512er_rcp28v16sf_mask = 2414,
  CODE_FOR_avx512er_rcp28v16sf_mask_round = 2415,
  CODE_FOR_avx512er_rcp28v8df_mask = 2418,
  CODE_FOR_avx512er_rcp28v8df_mask_round = 2419,
  CODE_FOR_avx512er_vmrcp28v4sf = 2420,
  CODE_FOR_avx512er_vmrcp28v4sf_round = 2421,
  CODE_FOR_avx512er_vmrcp28v2df = 2422,
  CODE_FOR_avx512er_vmrcp28v2df_round = 2423,
  CODE_FOR_avx512er_rsqrt28v16sf_mask = 2426,
  CODE_FOR_avx512er_rsqrt28v16sf_mask_round = 2427,
  CODE_FOR_avx512er_rsqrt28v8df_mask = 2430,
  CODE_FOR_avx512er_rsqrt28v8df_mask_round = 2431,
  CODE_FOR_avx512er_vmrsqrt28v4sf = 2432,
  CODE_FOR_avx512er_vmrsqrt28v4sf_round = 2433,
  CODE_FOR_avx512er_vmrsqrt28v2df = 2434,
  CODE_FOR_avx512er_vmrsqrt28v2df_round = 2435,
  CODE_FOR_xop_pmacsww = 2436,
  CODE_FOR_xop_pmacssww = 2437,
  CODE_FOR_xop_pmacsdd = 2438,
  CODE_FOR_xop_pmacssdd = 2439,
  CODE_FOR_xop_pmacsdql = 2440,
  CODE_FOR_xop_pmacssdql = 2441,
  CODE_FOR_xop_pmacsdqh = 2442,
  CODE_FOR_xop_pmacssdqh = 2443,
  CODE_FOR_xop_pmacswd = 2444,
  CODE_FOR_xop_pmacsswd = 2445,
  CODE_FOR_xop_pmadcswd = 2446,
  CODE_FOR_xop_pmadcsswd = 2447,
  CODE_FOR_xop_pcmov_v32qi256 = 2448,
  CODE_FOR_xop_pcmov_v16qi = 2449,
  CODE_FOR_xop_pcmov_v16hi256 = 2450,
  CODE_FOR_xop_pcmov_v8hi = 2451,
  CODE_FOR_xop_pcmov_v16si512 = 2452,
  CODE_FOR_xop_pcmov_v8si256 = 2453,
  CODE_FOR_xop_pcmov_v4si = 2454,
  CODE_FOR_xop_pcmov_v8di512 = 2455,
  CODE_FOR_xop_pcmov_v4di256 = 2456,
  CODE_FOR_xop_pcmov_v2di = 2457,
  CODE_FOR_xop_pcmov_v16sf512 = 2458,
  CODE_FOR_xop_pcmov_v8sf256 = 2459,
  CODE_FOR_xop_pcmov_v4sf = 2460,
  CODE_FOR_xop_pcmov_v8df512 = 2461,
  CODE_FOR_xop_pcmov_v4df256 = 2462,
  CODE_FOR_xop_pcmov_v2df = 2463,
  CODE_FOR_xop_phaddbw = 2464,
  CODE_FOR_xop_phaddubw = 2465,
  CODE_FOR_xop_phaddbd = 2466,
  CODE_FOR_xop_phaddubd = 2467,
  CODE_FOR_xop_phaddbq = 2468,
  CODE_FOR_xop_phaddubq = 2469,
  CODE_FOR_xop_phaddwd = 2470,
  CODE_FOR_xop_phadduwd = 2471,
  CODE_FOR_xop_phaddwq = 2472,
  CODE_FOR_xop_phadduwq = 2473,
  CODE_FOR_xop_phadddq = 2474,
  CODE_FOR_xop_phaddudq = 2475,
  CODE_FOR_xop_phsubbw = 2476,
  CODE_FOR_xop_phsubwd = 2477,
  CODE_FOR_xop_phsubdq = 2478,
  CODE_FOR_xop_pperm = 2479,
  CODE_FOR_xop_pperm_pack_v2di_v4si = 2480,
  CODE_FOR_xop_pperm_pack_v4si_v8hi = 2481,
  CODE_FOR_xop_pperm_pack_v8hi_v16qi = 2482,
  CODE_FOR_xop_rotlv16qi3 = 2483,
  CODE_FOR_xop_rotlv8hi3 = 2484,
  CODE_FOR_xop_rotlv4si3 = 2485,
  CODE_FOR_xop_rotlv2di3 = 2486,
  CODE_FOR_xop_rotrv16qi3 = 2487,
  CODE_FOR_xop_rotrv8hi3 = 2488,
  CODE_FOR_xop_rotrv4si3 = 2489,
  CODE_FOR_xop_rotrv2di3 = 2490,
  CODE_FOR_xop_vrotlv16qi3 = 2491,
  CODE_FOR_xop_vrotlv8hi3 = 2492,
  CODE_FOR_xop_vrotlv4si3 = 2493,
  CODE_FOR_xop_vrotlv2di3 = 2494,
  CODE_FOR_xop_shav16qi3 = 2495,
  CODE_FOR_xop_shav8hi3 = 2496,
  CODE_FOR_xop_shav4si3 = 2497,
  CODE_FOR_xop_shav2di3 = 2498,
  CODE_FOR_xop_shlv16qi3 = 2499,
  CODE_FOR_xop_shlv8hi3 = 2500,
  CODE_FOR_xop_shlv4si3 = 2501,
  CODE_FOR_xop_shlv2di3 = 2502,
  CODE_FOR_xop_frczsf2 = 2503,
  CODE_FOR_xop_frczdf2 = 2504,
  CODE_FOR_xop_frczv4sf2 = 2505,
  CODE_FOR_xop_frczv2df2 = 2506,
  CODE_FOR_xop_frczv8sf2 = 2507,
  CODE_FOR_xop_frczv4df2 = 2508,
  CODE_FOR_xop_frczv16sf2 = 2509,
  CODE_FOR_xop_frczv8df2 = 2510,
  CODE_FOR_xop_maskcmpv16qi3 = 2513,
  CODE_FOR_xop_maskcmpv8hi3 = 2514,
  CODE_FOR_xop_maskcmpv4si3 = 2515,
  CODE_FOR_xop_maskcmpv2di3 = 2516,
  CODE_FOR_xop_maskcmp_unsv16qi3 = 2517,
  CODE_FOR_xop_maskcmp_unsv8hi3 = 2518,
  CODE_FOR_xop_maskcmp_unsv4si3 = 2519,
  CODE_FOR_xop_maskcmp_unsv2di3 = 2520,
  CODE_FOR_xop_maskcmp_uns2v16qi3 = 2521,
  CODE_FOR_xop_maskcmp_uns2v8hi3 = 2522,
  CODE_FOR_xop_maskcmp_uns2v4si3 = 2523,
  CODE_FOR_xop_maskcmp_uns2v2di3 = 2524,
  CODE_FOR_xop_pcom_tfv16qi3 = 2525,
  CODE_FOR_xop_pcom_tfv8hi3 = 2526,
  CODE_FOR_xop_pcom_tfv4si3 = 2527,
  CODE_FOR_xop_pcom_tfv2di3 = 2528,
  CODE_FOR_xop_vpermil2v8sf3 = 2529,
  CODE_FOR_xop_vpermil2v4sf3 = 2530,
  CODE_FOR_xop_vpermil2v4df3 = 2531,
  CODE_FOR_xop_vpermil2v2df3 = 2532,
  CODE_FOR_aesenc = 2533,
  CODE_FOR_aesenclast = 2534,
  CODE_FOR_aesdec = 2535,
  CODE_FOR_aesdeclast = 2536,
  CODE_FOR_aesimc = 2537,
  CODE_FOR_aeskeygenassist = 2538,
  CODE_FOR_pclmulqdq = 2539,
  CODE_FOR_avx_vzeroupper = 2541,
  CODE_FOR_avx2_pbroadcastv16si = 2542,
  CODE_FOR_avx2_pbroadcastv8di = 2543,
  CODE_FOR_avx2_pbroadcastv32qi = 2544,
  CODE_FOR_avx2_pbroadcastv16qi = 2545,
  CODE_FOR_avx2_pbroadcastv16hi = 2546,
  CODE_FOR_avx2_pbroadcastv8hi = 2547,
  CODE_FOR_avx2_pbroadcastv8si = 2548,
  CODE_FOR_avx2_pbroadcastv4si = 2549,
  CODE_FOR_avx2_pbroadcastv4di = 2550,
  CODE_FOR_avx2_pbroadcastv2di = 2551,
  CODE_FOR_avx2_pbroadcastv32qi_1 = 2552,
  CODE_FOR_avx2_pbroadcastv16hi_1 = 2553,
  CODE_FOR_avx2_pbroadcastv8si_1 = 2554,
  CODE_FOR_avx2_pbroadcastv4di_1 = 2555,
  CODE_FOR_avx2_permvarv8si = 2556,
#define CODE_FOR_avx2_permvarv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_permvarv8sf = 2557,
#define CODE_FOR_avx2_permvarv8sf_mask CODE_FOR_nothing
  CODE_FOR_avx512f_permvarv16si = 2558,
  CODE_FOR_avx512f_permvarv16si_mask = 2559,
  CODE_FOR_avx512f_permvarv16sf = 2560,
  CODE_FOR_avx512f_permvarv16sf_mask = 2561,
  CODE_FOR_avx512f_permvarv8di = 2562,
  CODE_FOR_avx512f_permvarv8di_mask = 2563,
  CODE_FOR_avx512f_permvarv8df = 2564,
  CODE_FOR_avx512f_permvarv8df_mask = 2565,
  CODE_FOR_avx2_permv4di_1 = 2566,
#define CODE_FOR_avx2_permv4di_1_mask CODE_FOR_nothing
  CODE_FOR_avx2_permv4df_1 = 2567,
#define CODE_FOR_avx2_permv4df_1_mask CODE_FOR_nothing
  CODE_FOR_avx512f_permv8di_1 = 2568,
  CODE_FOR_avx512f_permv8di_1_mask = 2569,
  CODE_FOR_avx512f_permv8df_1 = 2570,
  CODE_FOR_avx512f_permv8df_1_mask = 2571,
  CODE_FOR_avx2_permv2ti = 2572,
  CODE_FOR_avx2_vec_dupv4df = 2573,
  CODE_FOR_vec_dupv8si = 2574,
  CODE_FOR_vec_dupv8sf = 2575,
  CODE_FOR_vec_dupv4di = 2576,
  CODE_FOR_vec_dupv4df = 2577,
  CODE_FOR_avx512f_vec_dupv16si_mask = 2579,
  CODE_FOR_avx512f_vec_dupv16sf_mask = 2581,
  CODE_FOR_avx512f_vec_dupv8di_mask = 2583,
  CODE_FOR_avx512f_vec_dupv8df_mask = 2585,
  CODE_FOR_avx512f_broadcastv16sf_mask = 2587,
  CODE_FOR_avx512f_broadcastv16si_mask = 2589,
  CODE_FOR_avx512f_broadcastv8df_mask = 2591,
  CODE_FOR_avx512f_broadcastv8di_mask = 2593,
  CODE_FOR_avx512f_vec_dup_gprv16si_mask = 2595,
#define CODE_FOR_avx512f_vec_dup_gprv8di_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vec_dup_memv16si_mask = 2597,
  CODE_FOR_avx512f_vec_dup_memv16sf_mask = 2599,
  CODE_FOR_avx512f_vec_dup_memv8di_mask = 2601,
  CODE_FOR_avx512f_vec_dup_memv8df_mask = 2603,
  CODE_FOR_avx2_vbroadcasti128_v32qi = 2604,
  CODE_FOR_avx2_vbroadcasti128_v16hi = 2605,
  CODE_FOR_avx2_vbroadcasti128_v8si = 2606,
  CODE_FOR_avx2_vbroadcasti128_v4di = 2607,
  CODE_FOR_avx_vbroadcastf128_v32qi = 2608,
  CODE_FOR_avx_vbroadcastf128_v16hi = 2609,
  CODE_FOR_avx_vbroadcastf128_v8si = 2610,
  CODE_FOR_avx_vbroadcastf128_v4di = 2611,
  CODE_FOR_avx_vbroadcastf128_v8sf = 2612,
  CODE_FOR_avx_vbroadcastf128_v4df = 2613,
  CODE_FOR_avx512cd_maskb_vec_dupv8di = 2614,
  CODE_FOR_avx512cd_maskw_vec_dupv16si = 2615,
  CODE_FOR_avx512f_vpermilvarv16sf3 = 2627,
  CODE_FOR_avx512f_vpermilvarv16sf3_mask = 2628,
  CODE_FOR_avx_vpermilvarv8sf3 = 2629,
#define CODE_FOR_avx_vpermilvarv8sf3_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilvarv4sf3 = 2630,
#define CODE_FOR_avx_vpermilvarv4sf3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermilvarv8df3 = 2631,
  CODE_FOR_avx512f_vpermilvarv8df3_mask = 2632,
  CODE_FOR_avx_vpermilvarv4df3 = 2633,
#define CODE_FOR_avx_vpermilvarv4df3_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilvarv2df3 = 2634,
#define CODE_FOR_avx_vpermilvarv2df3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermi2varv16si3 = 2635,
  CODE_FOR_avx512f_vpermi2varv16si3_maskz_1 = 2636,
  CODE_FOR_avx512f_vpermi2varv16sf3 = 2637,
  CODE_FOR_avx512f_vpermi2varv16sf3_maskz_1 = 2638,
  CODE_FOR_avx512f_vpermi2varv8di3 = 2639,
  CODE_FOR_avx512f_vpermi2varv8di3_maskz_1 = 2640,
  CODE_FOR_avx512f_vpermi2varv8df3 = 2641,
  CODE_FOR_avx512f_vpermi2varv8df3_maskz_1 = 2642,
  CODE_FOR_avx512f_vpermi2varv16si3_mask = 2643,
  CODE_FOR_avx512f_vpermi2varv16sf3_mask = 2644,
  CODE_FOR_avx512f_vpermi2varv8di3_mask = 2645,
  CODE_FOR_avx512f_vpermi2varv8df3_mask = 2646,
  CODE_FOR_avx512f_vpermt2varv16si3 = 2647,
  CODE_FOR_avx512f_vpermt2varv16si3_maskz_1 = 2648,
  CODE_FOR_avx512f_vpermt2varv16sf3 = 2649,
  CODE_FOR_avx512f_vpermt2varv16sf3_maskz_1 = 2650,
  CODE_FOR_avx512f_vpermt2varv8di3 = 2651,
  CODE_FOR_avx512f_vpermt2varv8di3_maskz_1 = 2652,
  CODE_FOR_avx512f_vpermt2varv8df3 = 2653,
  CODE_FOR_avx512f_vpermt2varv8df3_maskz_1 = 2654,
  CODE_FOR_avx512f_vpermt2varv16si3_mask = 2655,
  CODE_FOR_avx512f_vpermt2varv16sf3_mask = 2656,
  CODE_FOR_avx512f_vpermt2varv8di3_mask = 2657,
  CODE_FOR_avx512f_vpermt2varv8df3_mask = 2658,
  CODE_FOR_avx2_vec_set_lo_v4di = 2665,
  CODE_FOR_avx2_vec_set_hi_v4di = 2666,
  CODE_FOR_vec_set_lo_v4di = 2667,
  CODE_FOR_vec_set_lo_v4df = 2668,
  CODE_FOR_vec_set_hi_v4di = 2669,
  CODE_FOR_vec_set_hi_v4df = 2670,
  CODE_FOR_vec_set_lo_v8si = 2671,
  CODE_FOR_vec_set_lo_v8sf = 2672,
  CODE_FOR_vec_set_hi_v8si = 2673,
  CODE_FOR_vec_set_hi_v8sf = 2674,
  CODE_FOR_vec_set_lo_v16hi = 2675,
  CODE_FOR_vec_set_hi_v16hi = 2676,
  CODE_FOR_vec_set_lo_v32qi = 2677,
  CODE_FOR_vec_set_hi_v32qi = 2678,
  CODE_FOR_avx_maskloadps = 2679,
  CODE_FOR_avx_maskloadpd = 2680,
  CODE_FOR_avx_maskloadps256 = 2681,
  CODE_FOR_avx_maskloadpd256 = 2682,
  CODE_FOR_avx2_maskloadd = 2683,
  CODE_FOR_avx2_maskloadq = 2684,
  CODE_FOR_avx2_maskloadd256 = 2685,
  CODE_FOR_avx2_maskloadq256 = 2686,
  CODE_FOR_avx_maskstoreps = 2687,
  CODE_FOR_avx_maskstorepd = 2688,
  CODE_FOR_avx_maskstoreps256 = 2689,
  CODE_FOR_avx_maskstorepd256 = 2690,
  CODE_FOR_avx2_maskstored = 2691,
  CODE_FOR_avx2_maskstoreq = 2692,
  CODE_FOR_avx2_maskstored256 = 2693,
  CODE_FOR_avx2_maskstoreq256 = 2694,
  CODE_FOR_avx_si256_si = 2695,
  CODE_FOR_avx_ps256_ps = 2696,
  CODE_FOR_avx_pd256_pd = 2697,
  CODE_FOR_avx512f_ashrvv16si = 2698,
  CODE_FOR_avx512f_ashrvv16si_mask = 2699,
  CODE_FOR_avx2_ashrvv8si = 2700,
#define CODE_FOR_avx2_ashrvv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_ashrvv4si = 2701,
#define CODE_FOR_avx2_ashrvv4si_mask CODE_FOR_nothing
  CODE_FOR_avx512f_ashrvv8di = 2702,
  CODE_FOR_avx512f_ashrvv8di_mask = 2703,
  CODE_FOR_avx512f_ashlvv16si = 2704,
  CODE_FOR_avx512f_ashlvv16si_mask = 2705,
  CODE_FOR_avx512f_lshrvv16si = 2706,
  CODE_FOR_avx512f_lshrvv16si_mask = 2707,
  CODE_FOR_avx2_ashlvv8si = 2708,
#define CODE_FOR_avx2_ashlvv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv8si = 2709,
#define CODE_FOR_avx2_lshrvv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_ashlvv4si = 2710,
#define CODE_FOR_avx2_ashlvv4si_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv4si = 2711,
#define CODE_FOR_avx2_lshrvv4si_mask CODE_FOR_nothing
  CODE_FOR_avx512f_ashlvv8di = 2712,
  CODE_FOR_avx512f_ashlvv8di_mask = 2713,
  CODE_FOR_avx512f_lshrvv8di = 2714,
  CODE_FOR_avx512f_lshrvv8di_mask = 2715,
  CODE_FOR_avx2_ashlvv4di = 2716,
#define CODE_FOR_avx2_ashlvv4di_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv4di = 2717,
#define CODE_FOR_avx2_lshrvv4di_mask CODE_FOR_nothing
  CODE_FOR_avx2_ashlvv2di = 2718,
#define CODE_FOR_avx2_ashlvv2di_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv2di = 2719,
#define CODE_FOR_avx2_lshrvv2di_mask CODE_FOR_nothing
  CODE_FOR_avx_vec_concatv32qi = 2720,
  CODE_FOR_avx_vec_concatv16hi = 2721,
  CODE_FOR_avx_vec_concatv8si = 2722,
  CODE_FOR_avx_vec_concatv4di = 2723,
  CODE_FOR_avx_vec_concatv8sf = 2724,
  CODE_FOR_avx_vec_concatv4df = 2725,
  CODE_FOR_avx_vec_concatv64qi = 2726,
  CODE_FOR_avx_vec_concatv32hi = 2727,
  CODE_FOR_avx_vec_concatv16si = 2728,
  CODE_FOR_avx_vec_concatv8di = 2729,
  CODE_FOR_avx_vec_concatv16sf = 2730,
  CODE_FOR_avx_vec_concatv8df = 2731,
  CODE_FOR_vcvtph2ps = 2732,
  CODE_FOR_vcvtph2ps256 = 2734,
  CODE_FOR_avx512f_vcvtph2ps512_mask = 2737,
  CODE_FOR_avx512f_vcvtph2ps512_mask_round = 2738,
  CODE_FOR_vcvtps2ph256 = 2741,
  CODE_FOR_avx512f_vcvtps2ph512_mask = 2743,
  CODE_FOR_avx512f_compressv16si_mask = 2864,
  CODE_FOR_avx512f_compressv16sf_mask = 2865,
  CODE_FOR_avx512f_compressv8di_mask = 2866,
  CODE_FOR_avx512f_compressv8df_mask = 2867,
  CODE_FOR_avx512f_compressstorev16si_mask = 2868,
  CODE_FOR_avx512f_compressstorev16sf_mask = 2869,
  CODE_FOR_avx512f_compressstorev8di_mask = 2870,
  CODE_FOR_avx512f_compressstorev8df_mask = 2871,
  CODE_FOR_avx512f_expandv16si_mask = 2872,
  CODE_FOR_avx512f_expandv16sf_mask = 2873,
  CODE_FOR_avx512f_expandv8di_mask = 2874,
  CODE_FOR_avx512f_expandv8df_mask = 2875,
  CODE_FOR_avx512f_getmantv16sf = 2876,
  CODE_FOR_avx512f_getmantv16sf_round = 2877,
  CODE_FOR_avx512f_getmantv16sf_mask = 2878,
  CODE_FOR_avx512f_getmantv16sf_mask_round = 2879,
  CODE_FOR_avx512f_getmantv8df = 2880,
  CODE_FOR_avx512f_getmantv8df_round = 2881,
  CODE_FOR_avx512f_getmantv8df_mask = 2882,
  CODE_FOR_avx512f_getmantv8df_mask_round = 2883,
  CODE_FOR_avx512f_getmantv4sf = 2884,
  CODE_FOR_avx512f_getmantv4sf_round = 2885,
  CODE_FOR_avx512f_getmantv2df = 2886,
  CODE_FOR_avx512f_getmantv2df_round = 2887,
  CODE_FOR_clzv16si2 = 2888,
  CODE_FOR_clzv16si2_mask = 2889,
  CODE_FOR_clzv8di2 = 2890,
  CODE_FOR_clzv8di2_mask = 2891,
  CODE_FOR_conflictv16si_mask = 2893,
  CODE_FOR_conflictv8di_mask = 2895,
  CODE_FOR_sha1msg1 = 2896,
  CODE_FOR_sha1msg2 = 2897,
  CODE_FOR_sha1nexte = 2898,
  CODE_FOR_sha1rnds4 = 2899,
  CODE_FOR_sha256msg1 = 2900,
  CODE_FOR_sha256msg2 = 2901,
  CODE_FOR_sha256rnds2 = 2902,
  CODE_FOR_mfence_sse2 = 2905,
  CODE_FOR_mfence_nosse = 2906,
  CODE_FOR_atomic_loaddi_fpu = 2907,
  CODE_FOR_atomic_storeqi_1 = 2908,
  CODE_FOR_atomic_storehi_1 = 2909,
  CODE_FOR_atomic_storesi_1 = 2910,
#define CODE_FOR_atomic_storedi_1 CODE_FOR_nothing
  CODE_FOR_atomic_storedi_fpu = 2911,
  CODE_FOR_loaddi_via_fpu = 2912,
  CODE_FOR_storedi_via_fpu = 2913,
  CODE_FOR_atomic_compare_and_swapqi_1 = 2914,
  CODE_FOR_atomic_compare_and_swaphi_1 = 2915,
  CODE_FOR_atomic_compare_and_swapsi_1 = 2916,
#define CODE_FOR_atomic_compare_and_swapdi_1 CODE_FOR_nothing
  CODE_FOR_atomic_compare_and_swapdi_doubleword = 2917,
#define CODE_FOR_atomic_compare_and_swapti_doubleword CODE_FOR_nothing
  CODE_FOR_atomic_fetch_addqi = 2918,
  CODE_FOR_atomic_fetch_addhi = 2919,
  CODE_FOR_atomic_fetch_addsi = 2920,
#define CODE_FOR_atomic_fetch_adddi CODE_FOR_nothing
  CODE_FOR_atomic_exchangeqi = 2924,
  CODE_FOR_atomic_exchangehi = 2925,
  CODE_FOR_atomic_exchangesi = 2926,
#define CODE_FOR_atomic_exchangedi CODE_FOR_nothing
  CODE_FOR_atomic_addqi = 2927,
  CODE_FOR_atomic_addhi = 2928,
  CODE_FOR_atomic_addsi = 2929,
#define CODE_FOR_atomic_adddi CODE_FOR_nothing
  CODE_FOR_atomic_subqi = 2930,
  CODE_FOR_atomic_subhi = 2931,
  CODE_FOR_atomic_subsi = 2932,
#define CODE_FOR_atomic_subdi CODE_FOR_nothing
  CODE_FOR_atomic_andqi = 2933,
  CODE_FOR_atomic_orqi = 2934,
  CODE_FOR_atomic_xorqi = 2935,
  CODE_FOR_atomic_andhi = 2936,
  CODE_FOR_atomic_orhi = 2937,
  CODE_FOR_atomic_xorhi = 2938,
  CODE_FOR_atomic_andsi = 2939,
  CODE_FOR_atomic_orsi = 2940,
  CODE_FOR_atomic_xorsi = 2941,
#define CODE_FOR_atomic_anddi CODE_FOR_nothing
#define CODE_FOR_atomic_ordi CODE_FOR_nothing
#define CODE_FOR_atomic_xordi CODE_FOR_nothing
  CODE_FOR_cbranchqi4 = 2942,
  CODE_FOR_cbranchhi4 = 2943,
  CODE_FOR_cbranchsi4 = 2944,
  CODE_FOR_cbranchdi4 = 2945,
#define CODE_FOR_cbranchti4 CODE_FOR_nothing
  CODE_FOR_cstoreqi4 = 2946,
  CODE_FOR_cstorehi4 = 2947,
  CODE_FOR_cstoresi4 = 2948,
#define CODE_FOR_cstoredi4 CODE_FOR_nothing
  CODE_FOR_cmpsi_1 = 2949,
#define CODE_FOR_cmpdi_1 CODE_FOR_nothing
  CODE_FOR_cmpqi_ext_3 = 2950,
  CODE_FOR_cbranchxf4 = 2951,
  CODE_FOR_cstorexf4 = 2952,
  CODE_FOR_cbranchsf4 = 2953,
  CODE_FOR_cbranchdf4 = 2954,
  CODE_FOR_cstoresf4 = 2955,
  CODE_FOR_cstoredf4 = 2956,
  CODE_FOR_cbranchcc4 = 2957,
  CODE_FOR_cstorecc4 = 2958,
  CODE_FOR_movxi = 2975,
#define CODE_FOR_reload_noff_store CODE_FOR_nothing
#define CODE_FOR_reload_noff_load CODE_FOR_nothing
  CODE_FOR_movoi = 2976,
  CODE_FOR_movti = 2977,
  CODE_FOR_movcdi = 2978,
  CODE_FOR_movqi = 2979,
  CODE_FOR_movhi = 2980,
  CODE_FOR_movsi = 2981,
  CODE_FOR_movdi = 2982,
  CODE_FOR_movstrictqi = 2985,
  CODE_FOR_movstricthi = 2986,
  CODE_FOR_movtf = 2997,
  CODE_FOR_movsf = 2998,
  CODE_FOR_movdf = 2999,
  CODE_FOR_movxf = 3000,
  CODE_FOR_zero_extendsidi2 = 3007,
  CODE_FOR_zero_extendqisi2 = 3011,
  CODE_FOR_zero_extendhisi2 = 3012,
  CODE_FOR_zero_extendqihi2 = 3015,
  CODE_FOR_extendsidi2 = 3017,
  CODE_FOR_extendsfdf2 = 3028,
  CODE_FOR_extendsfxf2 = 3031,
  CODE_FOR_extenddfxf2 = 3032,
  CODE_FOR_truncdfsf2 = 3033,
  CODE_FOR_truncdfsf2_with_temp = 3036,
  CODE_FOR_truncxfsf2 = 3038,
  CODE_FOR_truncxfdf2 = 3039,
  CODE_FOR_fix_truncxfdi2 = 3044,
  CODE_FOR_fix_truncsfdi2 = 3045,
  CODE_FOR_fix_truncdfdi2 = 3046,
  CODE_FOR_fix_truncxfsi2 = 3047,
  CODE_FOR_fix_truncsfsi2 = 3048,
  CODE_FOR_fix_truncdfsi2 = 3049,
  CODE_FOR_fix_truncsfhi2 = 3050,
  CODE_FOR_fix_truncdfhi2 = 3051,
  CODE_FOR_fix_truncxfhi2 = 3052,
  CODE_FOR_fixuns_truncsfsi2 = 3053,
  CODE_FOR_fixuns_truncdfsi2 = 3054,
  CODE_FOR_fixuns_truncsfhi2 = 3057,
  CODE_FOR_fixuns_truncdfhi2 = 3058,
  CODE_FOR_floatsisf2 = 3081,
#define CODE_FOR_floatdisf2 CODE_FOR_nothing
  CODE_FOR_floatsidf2 = 3082,
#define CODE_FOR_floatdidf2 CODE_FOR_nothing
  CODE_FOR_floatunsqisf2 = 3097,
  CODE_FOR_floatunshisf2 = 3098,
  CODE_FOR_floatunsqidf2 = 3099,
  CODE_FOR_floatunshidf2 = 3100,
  CODE_FOR_floatunssisf2 = 3104,
  CODE_FOR_floatunssidf2 = 3105,
  CODE_FOR_floatunssixf2 = 3106,
#define CODE_FOR_floatunsdisf2 CODE_FOR_nothing
#define CODE_FOR_floatunsdidf2 CODE_FOR_nothing
  CODE_FOR_addqi3 = 3109,
  CODE_FOR_addhi3 = 3110,
  CODE_FOR_addsi3 = 3111,
  CODE_FOR_adddi3 = 3112,
#define CODE_FOR_addti3 CODE_FOR_nothing
  CODE_FOR_addvqi4 = 3120,
  CODE_FOR_addvhi4 = 3121,
  CODE_FOR_addvsi4 = 3122,
#define CODE_FOR_addvdi4 CODE_FOR_nothing
  CODE_FOR_subqi3 = 3128,
  CODE_FOR_subhi3 = 3129,
  CODE_FOR_subsi3 = 3130,
  CODE_FOR_subdi3 = 3131,
#define CODE_FOR_subti3 CODE_FOR_nothing
  CODE_FOR_subvqi4 = 3133,
  CODE_FOR_subvhi4 = 3134,
  CODE_FOR_subvsi4 = 3135,
#define CODE_FOR_subvdi4 CODE_FOR_nothing
  CODE_FOR_addqi3_carry = 3136,
  CODE_FOR_subqi3_carry = 3137,
  CODE_FOR_addhi3_carry = 3138,
  CODE_FOR_subhi3_carry = 3139,
  CODE_FOR_addsi3_carry = 3140,
  CODE_FOR_subsi3_carry = 3141,
  CODE_FOR_adddi3_carry = 3142,
  CODE_FOR_subdi3_carry = 3143,
  CODE_FOR_addxf3 = 3144,
  CODE_FOR_subxf3 = 3145,
  CODE_FOR_addsf3 = 3146,
  CODE_FOR_subsf3 = 3147,
  CODE_FOR_adddf3 = 3148,
  CODE_FOR_subdf3 = 3149,
  CODE_FOR_mulhi3 = 3150,
  CODE_FOR_mulsi3 = 3151,
#define CODE_FOR_muldi3 CODE_FOR_nothing
  CODE_FOR_mulqi3 = 3152,
  CODE_FOR_mulvsi4 = 3153,
#define CODE_FOR_mulvdi4 CODE_FOR_nothing
  CODE_FOR_mulsidi3 = 3154,
  CODE_FOR_umulsidi3 = 3155,
#define CODE_FOR_mulditi3 CODE_FOR_nothing
#define CODE_FOR_umulditi3 CODE_FOR_nothing
  CODE_FOR_mulqihi3 = 3156,
  CODE_FOR_umulqihi3 = 3157,
  CODE_FOR_smulsi3_highpart = 3160,
  CODE_FOR_umulsi3_highpart = 3161,
#define CODE_FOR_smuldi3_highpart CODE_FOR_nothing
#define CODE_FOR_umuldi3_highpart CODE_FOR_nothing
  CODE_FOR_mulxf3 = 3162,
  CODE_FOR_mulsf3 = 3163,
  CODE_FOR_muldf3 = 3164,
  CODE_FOR_divxf3 = 3165,
  CODE_FOR_divdf3 = 3166,
  CODE_FOR_divsf3 = 3167,
  CODE_FOR_divmodhi4 = 3168,
  CODE_FOR_divmodsi4 = 3169,
#define CODE_FOR_divmoddi4 CODE_FOR_nothing
  CODE_FOR_divmodqi4 = 3175,
  CODE_FOR_udivmodhi4 = 3176,
  CODE_FOR_udivmodsi4 = 3177,
#define CODE_FOR_udivmoddi4 CODE_FOR_nothing
  CODE_FOR_udivmodqi4 = 3183,
  CODE_FOR_testsi_ccno_1 = 3184,
  CODE_FOR_testqi_ccz_1 = 3185,
#define CODE_FOR_testdi_ccno_1 CODE_FOR_nothing
  CODE_FOR_testqi_ext_ccno_0 = 3186,
  CODE_FOR_andqi3 = 3196,
  CODE_FOR_andhi3 = 3197,
  CODE_FOR_andsi3 = 3198,
#define CODE_FOR_anddi3 CODE_FOR_nothing
  CODE_FOR_iorqi3 = 3209,
  CODE_FOR_xorqi3 = 3210,
  CODE_FOR_iorhi3 = 3211,
  CODE_FOR_xorhi3 = 3212,
  CODE_FOR_iorsi3 = 3213,
  CODE_FOR_xorsi3 = 3214,
#define CODE_FOR_iordi3 CODE_FOR_nothing
#define CODE_FOR_xordi3 CODE_FOR_nothing
  CODE_FOR_xorqi_cc_ext_1 = 3221,
  CODE_FOR_negqi2 = 3222,
  CODE_FOR_neghi2 = 3223,
  CODE_FOR_negsi2 = 3224,
  CODE_FOR_negdi2 = 3225,
#define CODE_FOR_negti2 CODE_FOR_nothing
  CODE_FOR_negvqi3 = 3227,
  CODE_FOR_negvhi3 = 3228,
  CODE_FOR_negvsi3 = 3229,
#define CODE_FOR_negvdi3 CODE_FOR_nothing
  CODE_FOR_abssf2 = 3230,
  CODE_FOR_negsf2 = 3231,
  CODE_FOR_absdf2 = 3232,
  CODE_FOR_negdf2 = 3233,
  CODE_FOR_absxf2 = 3234,
  CODE_FOR_negxf2 = 3235,
  CODE_FOR_abstf2 = 3236,
  CODE_FOR_negtf2 = 3237,
  CODE_FOR_copysignsf3 = 3243,
  CODE_FOR_copysigndf3 = 3244,
  CODE_FOR_copysigntf3 = 3245,
  CODE_FOR_one_cmplqi2 = 3252,
  CODE_FOR_one_cmplhi2 = 3253,
  CODE_FOR_one_cmplsi2 = 3254,
#define CODE_FOR_one_cmpldi2 CODE_FOR_nothing
  CODE_FOR_ashlqi3 = 3260,
  CODE_FOR_ashlhi3 = 3261,
  CODE_FOR_ashlsi3 = 3262,
  CODE_FOR_ashldi3 = 3263,
#define CODE_FOR_ashlti3 CODE_FOR_nothing
  CODE_FOR_x86_shiftsi_adj_1 = 3266,
#define CODE_FOR_x86_shiftdi_adj_1 CODE_FOR_nothing
  CODE_FOR_x86_shiftsi_adj_2 = 3267,
#define CODE_FOR_x86_shiftdi_adj_2 CODE_FOR_nothing
  CODE_FOR_lshrqi3 = 3270,
  CODE_FOR_ashrqi3 = 3271,
  CODE_FOR_lshrhi3 = 3272,
  CODE_FOR_ashrhi3 = 3273,
  CODE_FOR_lshrsi3 = 3274,
  CODE_FOR_ashrsi3 = 3275,
  CODE_FOR_lshrdi3 = 3276,
  CODE_FOR_ashrdi3 = 3277,
#define CODE_FOR_lshrti3 CODE_FOR_nothing
#define CODE_FOR_ashrti3 CODE_FOR_nothing
  CODE_FOR_x86_shiftsi_adj_3 = 3282,
#define CODE_FOR_x86_shiftdi_adj_3 CODE_FOR_nothing
#define CODE_FOR_rotlti3 CODE_FOR_nothing
#define CODE_FOR_rotrti3 CODE_FOR_nothing
  CODE_FOR_rotldi3 = 3285,
  CODE_FOR_rotrdi3 = 3286,
  CODE_FOR_rotlqi3 = 3287,
  CODE_FOR_rotrqi3 = 3288,
  CODE_FOR_rotlhi3 = 3289,
  CODE_FOR_rotrhi3 = 3290,
  CODE_FOR_rotlsi3 = 3291,
  CODE_FOR_rotrsi3 = 3292,
  CODE_FOR_extv = 3299,
  CODE_FOR_extzv = 3300,
  CODE_FOR_insv = 3301,
  CODE_FOR_indirect_jump = 3330,
  CODE_FOR_tablejump = 3331,
  CODE_FOR_call = 3336,
  CODE_FOR_sibcall = 3337,
  CODE_FOR_call_pop = 3338,
  CODE_FOR_call_value = 3339,
  CODE_FOR_sibcall_value = 3340,
  CODE_FOR_call_value_pop = 3341,
  CODE_FOR_untyped_call = 3342,
  CODE_FOR_memory_blockage = 3343,
  CODE_FOR_return = 3344,
  CODE_FOR_simple_return = 3345,
  CODE_FOR_prologue = 3346,
  CODE_FOR_epilogue = 3347,
  CODE_FOR_sibcall_epilogue = 3348,
  CODE_FOR_eh_return = 3349,
  CODE_FOR_split_stack_prologue = 3351,
  CODE_FOR_split_stack_space_check = 3352,
  CODE_FOR_ffssi2 = 3353,
#define CODE_FOR_ffsdi2 CODE_FOR_nothing
  CODE_FOR_ctzhi2 = 3355,
  CODE_FOR_ctzsi2 = 3356,
#define CODE_FOR_ctzdi2 CODE_FOR_nothing
  CODE_FOR_clzhi2 = 3359,
  CODE_FOR_clzsi2 = 3360,
#define CODE_FOR_clzdi2 CODE_FOR_nothing
  CODE_FOR_clzhi2_lzcnt = 3361,
  CODE_FOR_clzsi2_lzcnt = 3362,
#define CODE_FOR_clzdi2_lzcnt CODE_FOR_nothing
  CODE_FOR_popcounthi2 = 3365,
  CODE_FOR_popcountsi2 = 3366,
#define CODE_FOR_popcountdi2 CODE_FOR_nothing
#define CODE_FOR_bswapdi2 CODE_FOR_nothing
  CODE_FOR_bswapsi2 = 3369,
  CODE_FOR_paritydi2 = 3370,
  CODE_FOR_paritysi2 = 3371,
  CODE_FOR_tls_global_dynamic_32 = 3374,
#define CODE_FOR_tls_global_dynamic_64_si CODE_FOR_nothing
#define CODE_FOR_tls_global_dynamic_64_di CODE_FOR_nothing
  CODE_FOR_tls_local_dynamic_base_32 = 3375,
#define CODE_FOR_tls_local_dynamic_base_64_si CODE_FOR_nothing
#define CODE_FOR_tls_local_dynamic_base_64_di CODE_FOR_nothing
  CODE_FOR_tls_dynamic_gnu2_32 = 3377,
#define CODE_FOR_tls_dynamic_gnu2_64 CODE_FOR_nothing
  CODE_FOR_rsqrtsf2 = 3380,
  CODE_FOR_sqrtsf2 = 3381,
  CODE_FOR_sqrtdf2 = 3382,
  CODE_FOR_fmodxf3 = 3383,
  CODE_FOR_fmodsf3 = 3384,
  CODE_FOR_fmoddf3 = 3385,
  CODE_FOR_remainderxf3 = 3386,
  CODE_FOR_remaindersf3 = 3387,
  CODE_FOR_remainderdf3 = 3388,
  CODE_FOR_sincossf3 = 3395,
  CODE_FOR_sincosdf3 = 3396,
  CODE_FOR_tanxf2 = 3397,
  CODE_FOR_tansf2 = 3398,
  CODE_FOR_tandf2 = 3399,
  CODE_FOR_atan2xf3 = 3400,
  CODE_FOR_atan2sf3 = 3401,
  CODE_FOR_atan2df3 = 3402,
  CODE_FOR_atanxf2 = 3403,
  CODE_FOR_atansf2 = 3404,
  CODE_FOR_atandf2 = 3405,
  CODE_FOR_asinxf2 = 3406,
  CODE_FOR_asinsf2 = 3407,
  CODE_FOR_asindf2 = 3408,
  CODE_FOR_acosxf2 = 3409,
  CODE_FOR_acossf2 = 3410,
  CODE_FOR_acosdf2 = 3411,
  CODE_FOR_logxf2 = 3412,
  CODE_FOR_logsf2 = 3413,
  CODE_FOR_logdf2 = 3414,
  CODE_FOR_log10xf2 = 3415,
  CODE_FOR_log10sf2 = 3416,
  CODE_FOR_log10df2 = 3417,
  CODE_FOR_log2xf2 = 3418,
  CODE_FOR_log2sf2 = 3419,
  CODE_FOR_log2df2 = 3420,
  CODE_FOR_log1pxf2 = 3421,
  CODE_FOR_log1psf2 = 3422,
  CODE_FOR_log1pdf2 = 3423,
  CODE_FOR_logbxf2 = 3424,
  CODE_FOR_logbsf2 = 3425,
  CODE_FOR_logbdf2 = 3426,
  CODE_FOR_ilogbxf2 = 3427,
  CODE_FOR_ilogbsf2 = 3428,
  CODE_FOR_ilogbdf2 = 3429,
  CODE_FOR_expNcorexf3 = 3430,
  CODE_FOR_expxf2 = 3431,
  CODE_FOR_expsf2 = 3432,
  CODE_FOR_expdf2 = 3433,
  CODE_FOR_exp10xf2 = 3434,
  CODE_FOR_exp10sf2 = 3435,
  CODE_FOR_exp10df2 = 3436,
  CODE_FOR_exp2xf2 = 3437,
  CODE_FOR_exp2sf2 = 3438,
  CODE_FOR_exp2df2 = 3439,
  CODE_FOR_expm1xf2 = 3440,
  CODE_FOR_expm1sf2 = 3441,
  CODE_FOR_expm1df2 = 3442,
  CODE_FOR_ldexpxf3 = 3443,
  CODE_FOR_ldexpsf3 = 3444,
  CODE_FOR_ldexpdf3 = 3445,
  CODE_FOR_scalbxf3 = 3446,
  CODE_FOR_scalbsf3 = 3447,
  CODE_FOR_scalbdf3 = 3448,
  CODE_FOR_significandxf2 = 3449,
  CODE_FOR_significandsf2 = 3450,
  CODE_FOR_significanddf2 = 3451,
  CODE_FOR_rintsf2 = 3452,
  CODE_FOR_rintdf2 = 3453,
  CODE_FOR_roundsf2 = 3454,
  CODE_FOR_rounddf2 = 3455,
  CODE_FOR_roundxf2 = 3456,
  CODE_FOR_lrintxfhi2 = 3466,
  CODE_FOR_lrintxfsi2 = 3467,
  CODE_FOR_lrintxfdi2 = 3468,
  CODE_FOR_lrintsfsi2 = 3469,
#define CODE_FOR_lrintsfdi2 CODE_FOR_nothing
  CODE_FOR_lrintdfsi2 = 3470,
#define CODE_FOR_lrintdfdi2 CODE_FOR_nothing
  CODE_FOR_lroundsfhi2 = 3471,
  CODE_FOR_lrounddfhi2 = 3472,
  CODE_FOR_lroundxfhi2 = 3473,
  CODE_FOR_lroundsfsi2 = 3474,
  CODE_FOR_lrounddfsi2 = 3475,
  CODE_FOR_lroundxfsi2 = 3476,
  CODE_FOR_lroundsfdi2 = 3477,
  CODE_FOR_lrounddfdi2 = 3478,
  CODE_FOR_lroundxfdi2 = 3479,
  CODE_FOR_floorxf2 = 3483,
  CODE_FOR_ceilxf2 = 3484,
  CODE_FOR_btruncxf2 = 3485,
  CODE_FOR_floorsf2 = 3486,
  CODE_FOR_ceilsf2 = 3487,
  CODE_FOR_btruncsf2 = 3488,
  CODE_FOR_floordf2 = 3489,
  CODE_FOR_ceildf2 = 3490,
  CODE_FOR_btruncdf2 = 3491,
  CODE_FOR_nearbyintxf2 = 3493,
  CODE_FOR_nearbyintsf2 = 3494,
  CODE_FOR_nearbyintdf2 = 3495,
  CODE_FOR_lfloorxfhi2 = 3514,
  CODE_FOR_lceilxfhi2 = 3515,
  CODE_FOR_lfloorxfsi2 = 3516,
  CODE_FOR_lceilxfsi2 = 3517,
  CODE_FOR_lfloorxfdi2 = 3518,
  CODE_FOR_lceilxfdi2 = 3519,
  CODE_FOR_lfloorsfsi2 = 3520,
  CODE_FOR_lceilsfsi2 = 3521,
#define CODE_FOR_lfloorsfdi2 CODE_FOR_nothing
#define CODE_FOR_lceilsfdi2 CODE_FOR_nothing
  CODE_FOR_lfloordfsi2 = 3522,
  CODE_FOR_lceildfsi2 = 3523,
#define CODE_FOR_lfloordfdi2 CODE_FOR_nothing
#define CODE_FOR_lceildfdi2 CODE_FOR_nothing
  CODE_FOR_isinfxf2 = 3526,
  CODE_FOR_isinfsf2 = 3527,
  CODE_FOR_isinfdf2 = 3528,
  CODE_FOR_signbitxf2 = 3529,
  CODE_FOR_signbitdf2 = 3530,
  CODE_FOR_signbitsf2 = 3531,
  CODE_FOR_movmemsi = 3532,
#define CODE_FOR_movmemdi CODE_FOR_nothing
  CODE_FOR_strmov = 3533,
  CODE_FOR_strmov_singleop = 3534,
  CODE_FOR_rep_mov = 3535,
  CODE_FOR_setmemsi = 3536,
#define CODE_FOR_setmemdi CODE_FOR_nothing
  CODE_FOR_strset = 3537,
  CODE_FOR_strset_singleop = 3538,
  CODE_FOR_rep_stos = 3539,
  CODE_FOR_cmpstrnsi = 3540,
  CODE_FOR_cmpintqi = 3541,
  CODE_FOR_cmpstrnqi_nz_1 = 3542,
  CODE_FOR_cmpstrnqi_1 = 3543,
  CODE_FOR_strlensi = 3544,
  CODE_FOR_strlendi = 3545,
  CODE_FOR_strlenqi_1 = 3546,
  CODE_FOR_movqicc = 3549,
  CODE_FOR_movhicc = 3550,
  CODE_FOR_movsicc = 3551,
#define CODE_FOR_movdicc CODE_FOR_nothing
  CODE_FOR_x86_movsicc_0_m1 = 3552,
#define CODE_FOR_x86_movdicc_0_m1 CODE_FOR_nothing
  CODE_FOR_movsfcc = 3564,
  CODE_FOR_movdfcc = 3565,
  CODE_FOR_movxfcc = 3566,
  CODE_FOR_addqicc = 3573,
  CODE_FOR_addhicc = 3574,
  CODE_FOR_addsicc = 3575,
#define CODE_FOR_adddicc CODE_FOR_nothing
  CODE_FOR_allocate_stack = 3576,
  CODE_FOR_probe_stack = 3577,
  CODE_FOR_builtin_setjmp_receiver = 3578,
  CODE_FOR_prefetch = 3681,
  CODE_FOR_stack_protect_set = 3682,
  CODE_FOR_stack_protect_test = 3683,
  CODE_FOR_lwp_llwpcb = 3684,
  CODE_FOR_lwp_slwpcb = 3685,
  CODE_FOR_lwp_lwpvalsi3 = 3686,
#define CODE_FOR_lwp_lwpvaldi3 CODE_FOR_nothing
  CODE_FOR_lwp_lwpinssi3 = 3687,
#define CODE_FOR_lwp_lwpinsdi3 CODE_FOR_nothing
  CODE_FOR_pause = 3688,
  CODE_FOR_xbegin = 3689,
  CODE_FOR_xtest = 3690,
  CODE_FOR_movv8qi = 3691,
  CODE_FOR_movv4hi = 3692,
  CODE_FOR_movv2si = 3693,
  CODE_FOR_movv1di = 3694,
  CODE_FOR_movv2sf = 3695,
  CODE_FOR_movmisalignv8qi = 3701,
  CODE_FOR_movmisalignv4hi = 3702,
  CODE_FOR_movmisalignv2si = 3703,
  CODE_FOR_movmisalignv1di = 3704,
  CODE_FOR_movmisalignv2sf = 3705,
  CODE_FOR_mmx_addv2sf3 = 3706,
  CODE_FOR_mmx_subv2sf3 = 3707,
  CODE_FOR_mmx_subrv2sf3 = 3708,
  CODE_FOR_mmx_mulv2sf3 = 3709,
  CODE_FOR_mmx_smaxv2sf3 = 3710,
  CODE_FOR_mmx_sminv2sf3 = 3711,
  CODE_FOR_mmx_eqv2sf3 = 3712,
  CODE_FOR_vec_setv2sf = 3713,
  CODE_FOR_vec_extractv2sf = 3716,
  CODE_FOR_vec_initv2sf = 3717,
  CODE_FOR_mmx_addv8qi3 = 3718,
  CODE_FOR_mmx_subv8qi3 = 3719,
  CODE_FOR_mmx_addv4hi3 = 3720,
  CODE_FOR_mmx_subv4hi3 = 3721,
  CODE_FOR_mmx_addv2si3 = 3722,
  CODE_FOR_mmx_subv2si3 = 3723,
  CODE_FOR_mmx_addv1di3 = 3724,
  CODE_FOR_mmx_subv1di3 = 3725,
  CODE_FOR_mmx_ssaddv8qi3 = 3726,
  CODE_FOR_mmx_usaddv8qi3 = 3727,
  CODE_FOR_mmx_sssubv8qi3 = 3728,
  CODE_FOR_mmx_ussubv8qi3 = 3729,
  CODE_FOR_mmx_ssaddv4hi3 = 3730,
  CODE_FOR_mmx_usaddv4hi3 = 3731,
  CODE_FOR_mmx_sssubv4hi3 = 3732,
  CODE_FOR_mmx_ussubv4hi3 = 3733,
  CODE_FOR_mmx_mulv4hi3 = 3734,
  CODE_FOR_mmx_smulv4hi3_highpart = 3735,
  CODE_FOR_mmx_umulv4hi3_highpart = 3736,
  CODE_FOR_mmx_pmaddwd = 3737,
  CODE_FOR_mmx_pmulhrwv4hi3 = 3738,
  CODE_FOR_sse2_umulv1siv1di3 = 3739,
  CODE_FOR_mmx_smaxv4hi3 = 3740,
  CODE_FOR_mmx_sminv4hi3 = 3741,
  CODE_FOR_mmx_umaxv8qi3 = 3742,
  CODE_FOR_mmx_uminv8qi3 = 3743,
  CODE_FOR_mmx_eqv8qi3 = 3744,
  CODE_FOR_mmx_eqv4hi3 = 3745,
  CODE_FOR_mmx_eqv2si3 = 3746,
  CODE_FOR_mmx_andv8qi3 = 3747,
  CODE_FOR_mmx_iorv8qi3 = 3748,
  CODE_FOR_mmx_xorv8qi3 = 3749,
  CODE_FOR_mmx_andv4hi3 = 3750,
  CODE_FOR_mmx_iorv4hi3 = 3751,
  CODE_FOR_mmx_xorv4hi3 = 3752,
  CODE_FOR_mmx_andv2si3 = 3753,
  CODE_FOR_mmx_iorv2si3 = 3754,
  CODE_FOR_mmx_xorv2si3 = 3755,
  CODE_FOR_mmx_pinsrw = 3756,
  CODE_FOR_mmx_pshufw = 3757,
  CODE_FOR_vec_setv2si = 3758,
  CODE_FOR_vec_extractv2si = 3761,
  CODE_FOR_vec_initv2si = 3762,
  CODE_FOR_vec_setv4hi = 3763,
  CODE_FOR_vec_extractv4hi = 3764,
  CODE_FOR_vec_initv4hi = 3765,
  CODE_FOR_vec_setv8qi = 3766,
  CODE_FOR_vec_extractv8qi = 3767,
  CODE_FOR_vec_initv8qi = 3768,
  CODE_FOR_mmx_uavgv8qi3 = 3769,
  CODE_FOR_mmx_uavgv4hi3 = 3770,
  CODE_FOR_mmx_maskmovq = 3771,
  CODE_FOR_mmx_emms = 3772,
  CODE_FOR_mmx_femms = 3773,
  CODE_FOR_movv64qi = 3774,
  CODE_FOR_movv32qi = 3775,
  CODE_FOR_movv16qi = 3776,
  CODE_FOR_movv32hi = 3777,
  CODE_FOR_movv16hi = 3778,
  CODE_FOR_movv8hi = 3779,
  CODE_FOR_movv16si = 3780,
  CODE_FOR_movv8si = 3781,
  CODE_FOR_movv4si = 3782,
  CODE_FOR_movv8di = 3783,
  CODE_FOR_movv4di = 3784,
  CODE_FOR_movv2di = 3785,
  CODE_FOR_movv2ti = 3786,
  CODE_FOR_movv1ti = 3787,
  CODE_FOR_movv16sf = 3788,
  CODE_FOR_movv8sf = 3789,
  CODE_FOR_movv4sf = 3790,
  CODE_FOR_movv8df = 3791,
  CODE_FOR_movv4df = 3792,
  CODE_FOR_movv2df = 3793,
  CODE_FOR_movmisalignv64qi = 3797,
  CODE_FOR_movmisalignv32qi = 3798,
  CODE_FOR_movmisalignv16qi = 3799,
  CODE_FOR_movmisalignv32hi = 3800,
  CODE_FOR_movmisalignv16hi = 3801,
  CODE_FOR_movmisalignv8hi = 3802,
  CODE_FOR_movmisalignv16si = 3803,
  CODE_FOR_movmisalignv8si = 3804,
  CODE_FOR_movmisalignv4si = 3805,
  CODE_FOR_movmisalignv8di = 3806,
  CODE_FOR_movmisalignv4di = 3807,
  CODE_FOR_movmisalignv2di = 3808,
  CODE_FOR_movmisalignv2ti = 3809,
  CODE_FOR_movmisalignv1ti = 3810,
  CODE_FOR_movmisalignv16sf = 3811,
  CODE_FOR_movmisalignv8sf = 3812,
  CODE_FOR_movmisalignv4sf = 3813,
  CODE_FOR_movmisalignv8df = 3814,
  CODE_FOR_movmisalignv4df = 3815,
  CODE_FOR_movmisalignv2df = 3816,
  CODE_FOR_avx512f_loadups512 = 3817,
  CODE_FOR_avx512f_loadups512_mask = 3818,
  CODE_FOR_avx_loadups256 = 3819,
#define CODE_FOR_avx_loadups256_mask CODE_FOR_nothing
  CODE_FOR_sse_loadups = 3820,
#define CODE_FOR_sse_loadups_mask CODE_FOR_nothing
  CODE_FOR_avx512f_loadupd512 = 3821,
  CODE_FOR_avx512f_loadupd512_mask = 3822,
  CODE_FOR_avx_loadupd256 = 3823,
#define CODE_FOR_avx_loadupd256_mask CODE_FOR_nothing
  CODE_FOR_sse2_loadupd = 3824,
#define CODE_FOR_sse2_loadupd_mask CODE_FOR_nothing
  CODE_FOR_avx_loaddquv32qi = 3825,
  CODE_FOR_sse2_loaddquv16qi = 3826,
#define CODE_FOR_sse2_loaddquv16qi_mask CODE_FOR_nothing
  CODE_FOR_avx512f_loaddquv16si = 3827,
  CODE_FOR_avx512f_loaddquv16si_mask = 3828,
  CODE_FOR_avx512f_loaddquv8di = 3829,
  CODE_FOR_avx512f_loaddquv8di_mask = 3830,
#define CODE_FOR_storentdi CODE_FOR_nothing
  CODE_FOR_storentsi = 3831,
  CODE_FOR_storentsf = 3832,
  CODE_FOR_storentdf = 3833,
  CODE_FOR_storentv8di = 3834,
  CODE_FOR_storentv4di = 3835,
  CODE_FOR_storentv2di = 3836,
  CODE_FOR_storentv16sf = 3837,
  CODE_FOR_storentv8sf = 3838,
  CODE_FOR_storentv4sf = 3839,
  CODE_FOR_storentv8df = 3840,
  CODE_FOR_storentv4df = 3841,
  CODE_FOR_storentv2df = 3842,
  CODE_FOR_absv16sf2 = 3843,
  CODE_FOR_negv16sf2 = 3844,
  CODE_FOR_absv8sf2 = 3845,
  CODE_FOR_negv8sf2 = 3846,
  CODE_FOR_absv4sf2 = 3847,
  CODE_FOR_negv4sf2 = 3848,
  CODE_FOR_absv8df2 = 3849,
  CODE_FOR_negv8df2 = 3850,
  CODE_FOR_absv4df2 = 3851,
  CODE_FOR_negv4df2 = 3852,
  CODE_FOR_absv2df2 = 3853,
  CODE_FOR_negv2df2 = 3854,
  CODE_FOR_addv16sf3 = 3861,
  CODE_FOR_addv16sf3_round = 3862,
  CODE_FOR_addv16sf3_mask = 3863,
  CODE_FOR_addv16sf3_mask_round = 3864,
  CODE_FOR_subv16sf3 = 3865,
  CODE_FOR_subv16sf3_round = 3866,
  CODE_FOR_subv16sf3_mask = 3867,
  CODE_FOR_subv16sf3_mask_round = 3868,
  CODE_FOR_addv8sf3 = 3869,
#define CODE_FOR_addv8sf3_round CODE_FOR_nothing
#define CODE_FOR_addv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_addv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_subv8sf3 = 3870,
#define CODE_FOR_subv8sf3_round CODE_FOR_nothing
#define CODE_FOR_subv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_subv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_addv4sf3 = 3871,
#define CODE_FOR_addv4sf3_round CODE_FOR_nothing
#define CODE_FOR_addv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_addv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_subv4sf3 = 3872,
#define CODE_FOR_subv4sf3_round CODE_FOR_nothing
#define CODE_FOR_subv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_subv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_addv8df3 = 3873,
  CODE_FOR_addv8df3_round = 3874,
  CODE_FOR_addv8df3_mask = 3875,
  CODE_FOR_addv8df3_mask_round = 3876,
  CODE_FOR_subv8df3 = 3877,
  CODE_FOR_subv8df3_round = 3878,
  CODE_FOR_subv8df3_mask = 3879,
  CODE_FOR_subv8df3_mask_round = 3880,
  CODE_FOR_addv4df3 = 3881,
#define CODE_FOR_addv4df3_round CODE_FOR_nothing
#define CODE_FOR_addv4df3_mask CODE_FOR_nothing
#define CODE_FOR_addv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_subv4df3 = 3882,
#define CODE_FOR_subv4df3_round CODE_FOR_nothing
#define CODE_FOR_subv4df3_mask CODE_FOR_nothing
#define CODE_FOR_subv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_addv2df3 = 3883,
#define CODE_FOR_addv2df3_round CODE_FOR_nothing
#define CODE_FOR_addv2df3_mask CODE_FOR_nothing
#define CODE_FOR_addv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_subv2df3 = 3884,
#define CODE_FOR_subv2df3_round CODE_FOR_nothing
#define CODE_FOR_subv2df3_mask CODE_FOR_nothing
#define CODE_FOR_subv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv16sf3 = 3885,
  CODE_FOR_mulv16sf3_round = 3886,
  CODE_FOR_mulv16sf3_mask = 3887,
  CODE_FOR_mulv16sf3_mask_round = 3888,
  CODE_FOR_mulv8sf3 = 3889,
#define CODE_FOR_mulv8sf3_round CODE_FOR_nothing
#define CODE_FOR_mulv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_mulv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv4sf3 = 3890,
#define CODE_FOR_mulv4sf3_round CODE_FOR_nothing
#define CODE_FOR_mulv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_mulv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv8df3 = 3891,
  CODE_FOR_mulv8df3_round = 3892,
  CODE_FOR_mulv8df3_mask = 3893,
  CODE_FOR_mulv8df3_mask_round = 3894,
  CODE_FOR_mulv4df3 = 3895,
#define CODE_FOR_mulv4df3_round CODE_FOR_nothing
#define CODE_FOR_mulv4df3_mask CODE_FOR_nothing
#define CODE_FOR_mulv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv2df3 = 3896,
#define CODE_FOR_mulv2df3_round CODE_FOR_nothing
#define CODE_FOR_mulv2df3_mask CODE_FOR_nothing
#define CODE_FOR_mulv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_divv8df3 = 3897,
  CODE_FOR_divv4df3 = 3898,
  CODE_FOR_divv2df3 = 3899,
  CODE_FOR_divv16sf3 = 3900,
  CODE_FOR_divv8sf3 = 3901,
  CODE_FOR_divv4sf3 = 3902,
  CODE_FOR_sqrtv8df2 = 3903,
  CODE_FOR_sqrtv4df2 = 3904,
  CODE_FOR_sqrtv2df2 = 3905,
  CODE_FOR_sqrtv16sf2 = 3906,
  CODE_FOR_sqrtv8sf2 = 3907,
  CODE_FOR_sqrtv4sf2 = 3908,
  CODE_FOR_rsqrtv8sf2 = 3909,
  CODE_FOR_rsqrtv4sf2 = 3910,
  CODE_FOR_smaxv16sf3 = 3911,
  CODE_FOR_smaxv16sf3_round = 3912,
  CODE_FOR_smaxv16sf3_mask = 3913,
  CODE_FOR_smaxv16sf3_mask_round = 3914,
  CODE_FOR_sminv16sf3 = 3915,
  CODE_FOR_sminv16sf3_round = 3916,
  CODE_FOR_sminv16sf3_mask = 3917,
  CODE_FOR_sminv16sf3_mask_round = 3918,
  CODE_FOR_smaxv8sf3 = 3919,
#define CODE_FOR_smaxv8sf3_round CODE_FOR_nothing
#define CODE_FOR_smaxv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv8sf3 = 3920,
#define CODE_FOR_sminv8sf3_round CODE_FOR_nothing
#define CODE_FOR_sminv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_sminv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv4sf3 = 3921,
#define CODE_FOR_smaxv4sf3_round CODE_FOR_nothing
#define CODE_FOR_smaxv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv4sf3 = 3922,
#define CODE_FOR_sminv4sf3_round CODE_FOR_nothing
#define CODE_FOR_sminv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_sminv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv8df3 = 3923,
  CODE_FOR_smaxv8df3_round = 3924,
  CODE_FOR_smaxv8df3_mask = 3925,
  CODE_FOR_smaxv8df3_mask_round = 3926,
  CODE_FOR_sminv8df3 = 3927,
  CODE_FOR_sminv8df3_round = 3928,
  CODE_FOR_sminv8df3_mask = 3929,
  CODE_FOR_sminv8df3_mask_round = 3930,
  CODE_FOR_smaxv4df3 = 3931,
#define CODE_FOR_smaxv4df3_round CODE_FOR_nothing
#define CODE_FOR_smaxv4df3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv4df3 = 3932,
#define CODE_FOR_sminv4df3_round CODE_FOR_nothing
#define CODE_FOR_sminv4df3_mask CODE_FOR_nothing
#define CODE_FOR_sminv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv2df3 = 3933,
#define CODE_FOR_smaxv2df3_round CODE_FOR_nothing
#define CODE_FOR_smaxv2df3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv2df3 = 3934,
#define CODE_FOR_sminv2df3_round CODE_FOR_nothing
#define CODE_FOR_sminv2df3_mask CODE_FOR_nothing
#define CODE_FOR_sminv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_sse3_haddv2df3 = 3935,
  CODE_FOR_reduc_splus_v8df = 3936,
  CODE_FOR_reduc_splus_v4df = 3937,
  CODE_FOR_reduc_splus_v2df = 3938,
  CODE_FOR_reduc_splus_v16sf = 3939,
  CODE_FOR_reduc_splus_v8sf = 3940,
  CODE_FOR_reduc_splus_v4sf = 3941,
  CODE_FOR_reduc_smax_v32qi = 3942,
  CODE_FOR_reduc_smin_v32qi = 3943,
  CODE_FOR_reduc_smax_v16hi = 3944,
  CODE_FOR_reduc_smin_v16hi = 3945,
  CODE_FOR_reduc_smax_v8si = 3946,
  CODE_FOR_reduc_smin_v8si = 3947,
  CODE_FOR_reduc_smax_v4di = 3948,
  CODE_FOR_reduc_smin_v4di = 3949,
  CODE_FOR_reduc_smax_v8sf = 3950,
  CODE_FOR_reduc_smin_v8sf = 3951,
  CODE_FOR_reduc_smax_v4df = 3952,
  CODE_FOR_reduc_smin_v4df = 3953,
  CODE_FOR_reduc_smax_v4sf = 3954,
  CODE_FOR_reduc_smin_v4sf = 3955,
  CODE_FOR_reduc_smax_v16si = 3956,
  CODE_FOR_reduc_smin_v16si = 3957,
  CODE_FOR_reduc_smax_v8di = 3958,
  CODE_FOR_reduc_smin_v8di = 3959,
  CODE_FOR_reduc_smax_v16sf = 3960,
  CODE_FOR_reduc_smin_v16sf = 3961,
  CODE_FOR_reduc_smax_v8df = 3962,
  CODE_FOR_reduc_smin_v8df = 3963,
  CODE_FOR_reduc_umax_v16si = 3964,
  CODE_FOR_reduc_umin_v16si = 3965,
  CODE_FOR_reduc_umax_v8di = 3966,
  CODE_FOR_reduc_umin_v8di = 3967,
  CODE_FOR_reduc_umax_v32qi = 3968,
  CODE_FOR_reduc_umin_v32qi = 3969,
  CODE_FOR_reduc_umax_v16hi = 3970,
  CODE_FOR_reduc_umin_v16hi = 3971,
  CODE_FOR_reduc_umax_v8si = 3972,
  CODE_FOR_reduc_umin_v8si = 3973,
  CODE_FOR_reduc_umax_v4di = 3974,
  CODE_FOR_reduc_umin_v4di = 3975,
  CODE_FOR_reduc_umin_v8hi = 3976,
  CODE_FOR_vcondv64qiv16sf = 3977,
  CODE_FOR_vcondv32hiv16sf = 3978,
  CODE_FOR_vcondv16siv16sf = 3979,
  CODE_FOR_vcondv8div16sf = 3980,
  CODE_FOR_vcondv16sfv16sf = 3981,
  CODE_FOR_vcondv8dfv16sf = 3982,
  CODE_FOR_vcondv64qiv8df = 3983,
  CODE_FOR_vcondv32hiv8df = 3984,
  CODE_FOR_vcondv16siv8df = 3985,
  CODE_FOR_vcondv8div8df = 3986,
  CODE_FOR_vcondv16sfv8df = 3987,
  CODE_FOR_vcondv8dfv8df = 3988,
  CODE_FOR_vcondv32qiv8sf = 3989,
  CODE_FOR_vcondv32qiv4df = 3990,
  CODE_FOR_vcondv16hiv8sf = 3991,
  CODE_FOR_vcondv16hiv4df = 3992,
  CODE_FOR_vcondv8siv8sf = 3993,
  CODE_FOR_vcondv8siv4df = 3994,
  CODE_FOR_vcondv4div8sf = 3995,
  CODE_FOR_vcondv4div4df = 3996,
  CODE_FOR_vcondv8sfv8sf = 3997,
  CODE_FOR_vcondv8sfv4df = 3998,
  CODE_FOR_vcondv4dfv8sf = 3999,
  CODE_FOR_vcondv4dfv4df = 4000,
  CODE_FOR_vcondv16qiv4sf = 4001,
  CODE_FOR_vcondv16qiv2df = 4002,
  CODE_FOR_vcondv8hiv4sf = 4003,
  CODE_FOR_vcondv8hiv2df = 4004,
  CODE_FOR_vcondv4siv4sf = 4005,
  CODE_FOR_vcondv4siv2df = 4006,
  CODE_FOR_vcondv2div4sf = 4007,
  CODE_FOR_vcondv2div2df = 4008,
  CODE_FOR_vcondv4sfv4sf = 4009,
  CODE_FOR_vcondv4sfv2df = 4010,
  CODE_FOR_vcondv2dfv4sf = 4011,
  CODE_FOR_vcondv2dfv2df = 4012,
  CODE_FOR_andv8sf3 = 4013,
  CODE_FOR_iorv8sf3 = 4014,
  CODE_FOR_xorv8sf3 = 4015,
  CODE_FOR_andv4sf3 = 4016,
  CODE_FOR_iorv4sf3 = 4017,
  CODE_FOR_xorv4sf3 = 4018,
  CODE_FOR_andv4df3 = 4019,
  CODE_FOR_iorv4df3 = 4020,
  CODE_FOR_xorv4df3 = 4021,
  CODE_FOR_andv2df3 = 4022,
  CODE_FOR_iorv2df3 = 4023,
  CODE_FOR_xorv2df3 = 4024,
  CODE_FOR_andv16sf3 = 4025,
  CODE_FOR_xorv16sf3 = 4026,
  CODE_FOR_andv8df3 = 4027,
  CODE_FOR_xorv8df3 = 4028,
  CODE_FOR_copysignv16sf3 = 4029,
  CODE_FOR_copysignv8sf3 = 4030,
  CODE_FOR_copysignv4sf3 = 4031,
  CODE_FOR_copysignv8df3 = 4032,
  CODE_FOR_copysignv4df3 = 4033,
  CODE_FOR_copysignv2df3 = 4034,
  CODE_FOR_andtf3 = 4035,
  CODE_FOR_iortf3 = 4036,
  CODE_FOR_xortf3 = 4037,
  CODE_FOR_fmasf4 = 4038,
  CODE_FOR_fmadf4 = 4039,
  CODE_FOR_fmav4sf4 = 4040,
  CODE_FOR_fmav2df4 = 4041,
  CODE_FOR_fmav8sf4 = 4042,
  CODE_FOR_fmav4df4 = 4043,
  CODE_FOR_fmav16sf4 = 4044,
  CODE_FOR_fmav8df4 = 4045,
  CODE_FOR_fmssf4 = 4046,
  CODE_FOR_fmsdf4 = 4047,
  CODE_FOR_fmsv4sf4 = 4048,
  CODE_FOR_fmsv2df4 = 4049,
  CODE_FOR_fmsv8sf4 = 4050,
  CODE_FOR_fmsv4df4 = 4051,
  CODE_FOR_fmsv16sf4 = 4052,
  CODE_FOR_fmsv8df4 = 4053,
  CODE_FOR_fnmasf4 = 4054,
  CODE_FOR_fnmadf4 = 4055,
  CODE_FOR_fnmav4sf4 = 4056,
  CODE_FOR_fnmav2df4 = 4057,
  CODE_FOR_fnmav8sf4 = 4058,
  CODE_FOR_fnmav4df4 = 4059,
  CODE_FOR_fnmav16sf4 = 4060,
  CODE_FOR_fnmav8df4 = 4061,
  CODE_FOR_fnmssf4 = 4062,
  CODE_FOR_fnmsdf4 = 4063,
  CODE_FOR_fnmsv4sf4 = 4064,
  CODE_FOR_fnmsv2df4 = 4065,
  CODE_FOR_fnmsv8sf4 = 4066,
  CODE_FOR_fnmsv4df4 = 4067,
  CODE_FOR_fnmsv16sf4 = 4068,
  CODE_FOR_fnmsv8df4 = 4069,
  CODE_FOR_fma4i_fmadd_sf = 4070,
  CODE_FOR_fma4i_fmadd_df = 4071,
  CODE_FOR_fma4i_fmadd_v4sf = 4072,
  CODE_FOR_fma4i_fmadd_v2df = 4073,
  CODE_FOR_fma4i_fmadd_v8sf = 4074,
  CODE_FOR_fma4i_fmadd_v4df = 4075,
  CODE_FOR_fma4i_fmadd_v16sf = 4076,
  CODE_FOR_fma4i_fmadd_v8df = 4077,
  CODE_FOR_avx512f_fmadd_v16sf_maskz = 4078,
  CODE_FOR_avx512f_fmadd_v16sf_maskz_round = 4079,
  CODE_FOR_avx512f_fmadd_v8df_maskz = 4080,
  CODE_FOR_avx512f_fmadd_v8df_maskz_round = 4081,
  CODE_FOR_fmaddsub_v16sf = 4082,
  CODE_FOR_fmaddsub_v8sf = 4083,
  CODE_FOR_fmaddsub_v4sf = 4084,
  CODE_FOR_fmaddsub_v8df = 4085,
  CODE_FOR_fmaddsub_v4df = 4086,
  CODE_FOR_fmaddsub_v2df = 4087,
  CODE_FOR_avx512f_fmaddsub_v16sf_maskz = 4088,
  CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round = 4089,
  CODE_FOR_avx512f_fmaddsub_v8df_maskz = 4090,
  CODE_FOR_avx512f_fmaddsub_v8df_maskz_round = 4091,
  CODE_FOR_fmai_vmfmadd_v4sf = 4092,
  CODE_FOR_fmai_vmfmadd_v4sf_round = 4093,
  CODE_FOR_fmai_vmfmadd_v2df = 4094,
  CODE_FOR_fmai_vmfmadd_v2df_round = 4095,
  CODE_FOR_fma4i_vmfmadd_v4sf = 4096,
  CODE_FOR_fma4i_vmfmadd_v2df = 4097,
  CODE_FOR_floatunsv16siv16sf2 = 4098,
  CODE_FOR_floatunsv8siv8sf2 = 4099,
  CODE_FOR_floatunsv4siv4sf2 = 4100,
  CODE_FOR_fixuns_truncv16sfv16si2 = 4101,
  CODE_FOR_fixuns_truncv8sfv8si2 = 4102,
  CODE_FOR_fixuns_truncv4sfv4si2 = 4103,
  CODE_FOR_avx_cvtpd2dq256_2 = 4104,
  CODE_FOR_sse2_cvtpd2dq = 4105,
  CODE_FOR_avx_cvttpd2dq256_2 = 4106,
  CODE_FOR_sse2_cvttpd2dq = 4107,
  CODE_FOR_sse2_cvtpd2ps = 4108,
  CODE_FOR_vec_unpacks_hi_v4sf = 4109,
  CODE_FOR_vec_unpacks_hi_v8sf = 4110,
  CODE_FOR_vec_unpacks_hi_v16sf = 4111,
  CODE_FOR_vec_unpacks_lo_v4sf = 4112,
  CODE_FOR_vec_unpacks_lo_v8sf = 4113,
  CODE_FOR_vec_unpacks_float_hi_v32hi = 4114,
  CODE_FOR_vec_unpacks_float_hi_v16hi = 4115,
  CODE_FOR_vec_unpacks_float_hi_v8hi = 4116,
  CODE_FOR_vec_unpacks_float_lo_v32hi = 4117,
  CODE_FOR_vec_unpacks_float_lo_v16hi = 4118,
  CODE_FOR_vec_unpacks_float_lo_v8hi = 4119,
  CODE_FOR_vec_unpacku_float_hi_v32hi = 4120,
  CODE_FOR_vec_unpacku_float_hi_v16hi = 4121,
  CODE_FOR_vec_unpacku_float_hi_v8hi = 4122,
  CODE_FOR_vec_unpacku_float_lo_v32hi = 4123,
  CODE_FOR_vec_unpacku_float_lo_v16hi = 4124,
  CODE_FOR_vec_unpacku_float_lo_v8hi = 4125,
  CODE_FOR_vec_unpacks_float_hi_v4si = 4126,
  CODE_FOR_vec_unpacks_float_lo_v4si = 4127,
  CODE_FOR_vec_unpacks_float_hi_v8si = 4128,
  CODE_FOR_vec_unpacks_float_lo_v8si = 4129,
  CODE_FOR_vec_unpacks_float_hi_v16si = 4130,
  CODE_FOR_vec_unpacks_float_lo_v16si = 4131,
  CODE_FOR_vec_unpacku_float_hi_v4si = 4132,
  CODE_FOR_vec_unpacku_float_lo_v4si = 4133,
  CODE_FOR_vec_unpacku_float_hi_v8si = 4134,
  CODE_FOR_vec_unpacku_float_hi_v16si = 4135,
  CODE_FOR_vec_unpacku_float_lo_v8si = 4136,
  CODE_FOR_vec_unpacku_float_lo_v16si = 4137,
  CODE_FOR_vec_pack_trunc_v8df = 4138,
  CODE_FOR_vec_pack_trunc_v4df = 4139,
  CODE_FOR_vec_pack_trunc_v2df = 4140,
  CODE_FOR_vec_pack_sfix_trunc_v8df = 4141,
  CODE_FOR_vec_pack_sfix_trunc_v4df = 4142,
  CODE_FOR_vec_pack_sfix_trunc_v2df = 4143,
  CODE_FOR_vec_pack_ufix_trunc_v8df = 4144,
  CODE_FOR_vec_pack_ufix_trunc_v4df = 4145,
  CODE_FOR_vec_pack_ufix_trunc_v2df = 4146,
  CODE_FOR_vec_pack_sfix_v4df = 4147,
  CODE_FOR_vec_pack_sfix_v2df = 4148,
  CODE_FOR_sse_movhlps_exp = 4149,
  CODE_FOR_sse_movlhps_exp = 4150,
  CODE_FOR_vec_interleave_highv8sf = 4151,
  CODE_FOR_vec_interleave_lowv8sf = 4152,
  CODE_FOR_avx_shufps256 = 4153,
  CODE_FOR_sse_shufps = 4154,
  CODE_FOR_sse_loadhps_exp = 4155,
  CODE_FOR_sse_loadlps_exp = 4156,
  CODE_FOR_vec_initv16qi = 4157,
  CODE_FOR_vec_initv8hi = 4158,
  CODE_FOR_vec_initv4si = 4159,
  CODE_FOR_vec_initv2di = 4160,
  CODE_FOR_vec_initv4sf = 4161,
  CODE_FOR_vec_initv2df = 4162,
  CODE_FOR_vec_setv32qi = 4165,
  CODE_FOR_vec_setv16qi = 4166,
  CODE_FOR_vec_setv16hi = 4167,
  CODE_FOR_vec_setv8hi = 4168,
  CODE_FOR_vec_setv16si = 4169,
  CODE_FOR_vec_setv8si = 4170,
  CODE_FOR_vec_setv4si = 4171,
  CODE_FOR_vec_setv8di = 4172,
  CODE_FOR_vec_setv4di = 4173,
  CODE_FOR_vec_setv2di = 4174,
  CODE_FOR_vec_setv16sf = 4175,
  CODE_FOR_vec_setv8sf = 4176,
  CODE_FOR_vec_setv4sf = 4177,
  CODE_FOR_vec_setv8df = 4178,
  CODE_FOR_vec_setv4df = 4179,
  CODE_FOR_vec_setv2df = 4180,
  CODE_FOR_avx512f_vextractf32x4_mask = 4184,
  CODE_FOR_avx512f_vextracti32x4_mask = 4185,
  CODE_FOR_avx512f_vextractf64x4_mask = 4186,
  CODE_FOR_avx512f_vextracti64x4_mask = 4187,
  CODE_FOR_avx_vextractf128v32qi = 4190,
  CODE_FOR_avx_vextractf128v16hi = 4191,
  CODE_FOR_avx_vextractf128v8si = 4192,
  CODE_FOR_avx_vextractf128v4di = 4193,
  CODE_FOR_avx_vextractf128v8sf = 4194,
  CODE_FOR_avx_vextractf128v4df = 4195,
  CODE_FOR_vec_extractv32qi = 4206,
  CODE_FOR_vec_extractv16qi = 4207,
  CODE_FOR_vec_extractv16hi = 4208,
  CODE_FOR_vec_extractv8hi = 4209,
  CODE_FOR_vec_extractv16si = 4210,
  CODE_FOR_vec_extractv8si = 4211,
  CODE_FOR_vec_extractv4si = 4212,
  CODE_FOR_vec_extractv8di = 4213,
  CODE_FOR_vec_extractv4di = 4214,
  CODE_FOR_vec_extractv2di = 4215,
  CODE_FOR_vec_extractv16sf = 4216,
  CODE_FOR_vec_extractv8sf = 4217,
  CODE_FOR_vec_extractv4sf = 4218,
  CODE_FOR_vec_extractv8df = 4219,
  CODE_FOR_vec_extractv4df = 4220,
  CODE_FOR_vec_extractv2df = 4221,
  CODE_FOR_vec_interleave_highv4df = 4222,
  CODE_FOR_vec_interleave_highv2df = 4223,
  CODE_FOR_avx512f_movddup512 = 4224,
  CODE_FOR_avx512f_movddup512_mask = 4225,
  CODE_FOR_avx512f_unpcklpd512 = 4226,
  CODE_FOR_avx512f_unpcklpd512_mask = 4227,
  CODE_FOR_avx_movddup256 = 4228,
  CODE_FOR_avx_unpcklpd256 = 4229,
  CODE_FOR_vec_interleave_lowv4df = 4230,
  CODE_FOR_vec_interleave_lowv2df = 4231,
  CODE_FOR_avx512f_vternlogv16si_maskz = 4234,
  CODE_FOR_avx512f_vternlogv8di_maskz = 4235,
  CODE_FOR_avx512f_shufps512_mask = 4236,
  CODE_FOR_avx512f_fixupimmv16sf_maskz = 4237,
  CODE_FOR_avx512f_fixupimmv16sf_maskz_round = 4238,
  CODE_FOR_avx512f_fixupimmv8df_maskz = 4239,
  CODE_FOR_avx512f_fixupimmv8df_maskz_round = 4240,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz = 4241,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz_round = 4242,
  CODE_FOR_avx512f_sfixupimmv2df_maskz = 4243,
  CODE_FOR_avx512f_sfixupimmv2df_maskz_round = 4244,
  CODE_FOR_avx512f_shufpd512_mask = 4245,
  CODE_FOR_avx_shufpd256 = 4246,
  CODE_FOR_sse2_shufpd = 4247,
  CODE_FOR_sse2_loadhpd_exp = 4250,
  CODE_FOR_sse2_loadlpd_exp = 4252,
  CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store = 4254,
  CODE_FOR_avx512f_truncatev16siv16qi2_mask_store = 4255,
  CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store = 4256,
  CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store = 4257,
  CODE_FOR_avx512f_truncatev16siv16hi2_mask_store = 4258,
  CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store = 4259,
  CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store = 4260,
  CODE_FOR_avx512f_truncatev8div8si2_mask_store = 4261,
  CODE_FOR_avx512f_us_truncatev8div8si2_mask_store = 4262,
  CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store = 4263,
  CODE_FOR_avx512f_truncatev8div8hi2_mask_store = 4264,
  CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store = 4265,
  CODE_FOR_negv32qi2 = 4266,
  CODE_FOR_negv16qi2 = 4267,
  CODE_FOR_negv16hi2 = 4268,
  CODE_FOR_negv8hi2 = 4269,
  CODE_FOR_negv16si2 = 4270,
  CODE_FOR_negv8si2 = 4271,
  CODE_FOR_negv4si2 = 4272,
  CODE_FOR_negv8di2 = 4273,
  CODE_FOR_negv4di2 = 4274,
  CODE_FOR_negv2di2 = 4275,
  CODE_FOR_addv32qi3 = 4276,
  CODE_FOR_subv32qi3 = 4277,
  CODE_FOR_addv16qi3 = 4278,
#define CODE_FOR_addv16qi3_mask CODE_FOR_nothing
  CODE_FOR_subv16qi3 = 4279,
#define CODE_FOR_subv16qi3_mask CODE_FOR_nothing
  CODE_FOR_addv16hi3 = 4280,
#define CODE_FOR_addv16hi3_mask CODE_FOR_nothing
  CODE_FOR_subv16hi3 = 4281,
#define CODE_FOR_subv16hi3_mask CODE_FOR_nothing
  CODE_FOR_addv8hi3 = 4282,
#define CODE_FOR_addv8hi3_mask CODE_FOR_nothing
  CODE_FOR_subv8hi3 = 4283,
#define CODE_FOR_subv8hi3_mask CODE_FOR_nothing
  CODE_FOR_addv16si3 = 4284,
  CODE_FOR_addv16si3_mask = 4285,
  CODE_FOR_subv16si3 = 4286,
  CODE_FOR_subv16si3_mask = 4287,
  CODE_FOR_addv8si3 = 4288,
#define CODE_FOR_addv8si3_mask CODE_FOR_nothing
  CODE_FOR_subv8si3 = 4289,
#define CODE_FOR_subv8si3_mask CODE_FOR_nothing
  CODE_FOR_addv4si3 = 4290,
#define CODE_FOR_addv4si3_mask CODE_FOR_nothing
  CODE_FOR_subv4si3 = 4291,
#define CODE_FOR_subv4si3_mask CODE_FOR_nothing
  CODE_FOR_addv8di3 = 4292,
  CODE_FOR_addv8di3_mask = 4293,
  CODE_FOR_subv8di3 = 4294,
  CODE_FOR_subv8di3_mask = 4295,
  CODE_FOR_addv4di3 = 4296,
#define CODE_FOR_addv4di3_mask CODE_FOR_nothing
  CODE_FOR_subv4di3 = 4297,
#define CODE_FOR_subv4di3_mask CODE_FOR_nothing
  CODE_FOR_addv2di3 = 4298,
#define CODE_FOR_addv2di3_mask CODE_FOR_nothing
  CODE_FOR_subv2di3 = 4299,
#define CODE_FOR_subv2di3_mask CODE_FOR_nothing
  CODE_FOR_avx2_ssaddv32qi3 = 4300,
  CODE_FOR_avx2_usaddv32qi3 = 4301,
  CODE_FOR_avx2_sssubv32qi3 = 4302,
  CODE_FOR_avx2_ussubv32qi3 = 4303,
  CODE_FOR_sse2_ssaddv16qi3 = 4304,
  CODE_FOR_sse2_usaddv16qi3 = 4305,
  CODE_FOR_sse2_sssubv16qi3 = 4306,
  CODE_FOR_sse2_ussubv16qi3 = 4307,
  CODE_FOR_avx2_ssaddv16hi3 = 4308,
  CODE_FOR_avx2_usaddv16hi3 = 4309,
  CODE_FOR_avx2_sssubv16hi3 = 4310,
  CODE_FOR_avx2_ussubv16hi3 = 4311,
  CODE_FOR_sse2_ssaddv8hi3 = 4312,
  CODE_FOR_sse2_usaddv8hi3 = 4313,
  CODE_FOR_sse2_sssubv8hi3 = 4314,
  CODE_FOR_sse2_ussubv8hi3 = 4315,
  CODE_FOR_mulv32qi3 = 4316,
  CODE_FOR_mulv16qi3 = 4317,
  CODE_FOR_mulv16hi3 = 4318,
  CODE_FOR_mulv8hi3 = 4319,
  CODE_FOR_smulv16hi3_highpart = 4320,
  CODE_FOR_umulv16hi3_highpart = 4321,
  CODE_FOR_smulv8hi3_highpart = 4322,
  CODE_FOR_umulv8hi3_highpart = 4323,
  CODE_FOR_vec_widen_umult_even_v16si = 4324,
  CODE_FOR_vec_widen_umult_even_v16si_mask = 4325,
  CODE_FOR_vec_widen_umult_even_v8si = 4326,
  CODE_FOR_vec_widen_umult_even_v4si = 4327,
  CODE_FOR_vec_widen_smult_even_v16si = 4328,
  CODE_FOR_vec_widen_smult_even_v16si_mask = 4329,
  CODE_FOR_vec_widen_smult_even_v8si = 4330,
  CODE_FOR_sse4_1_mulv2siv2di3 = 4331,
  CODE_FOR_avx2_pmaddwd = 4332,
  CODE_FOR_sse2_pmaddwd = 4333,
  CODE_FOR_mulv16si3 = 4334,
  CODE_FOR_mulv16si3_mask = 4335,
  CODE_FOR_mulv8si3 = 4336,
#define CODE_FOR_mulv8si3_mask CODE_FOR_nothing
  CODE_FOR_mulv4si3 = 4337,
#define CODE_FOR_mulv4si3_mask CODE_FOR_nothing
  CODE_FOR_mulv8di3 = 4338,
  CODE_FOR_mulv4di3 = 4339,
  CODE_FOR_mulv2di3 = 4340,
  CODE_FOR_vec_widen_smult_hi_v32qi = 4341,
  CODE_FOR_vec_widen_umult_hi_v32qi = 4342,
  CODE_FOR_vec_widen_smult_hi_v16qi = 4343,
  CODE_FOR_vec_widen_umult_hi_v16qi = 4344,
  CODE_FOR_vec_widen_smult_hi_v16hi = 4345,
  CODE_FOR_vec_widen_umult_hi_v16hi = 4346,
  CODE_FOR_vec_widen_smult_hi_v8hi = 4347,
  CODE_FOR_vec_widen_umult_hi_v8hi = 4348,
  CODE_FOR_vec_widen_smult_hi_v8si = 4349,
  CODE_FOR_vec_widen_umult_hi_v8si = 4350,
  CODE_FOR_vec_widen_smult_hi_v4si = 4351,
  CODE_FOR_vec_widen_umult_hi_v4si = 4352,
  CODE_FOR_vec_widen_smult_lo_v32qi = 4353,
  CODE_FOR_vec_widen_umult_lo_v32qi = 4354,
  CODE_FOR_vec_widen_smult_lo_v16qi = 4355,
  CODE_FOR_vec_widen_umult_lo_v16qi = 4356,
  CODE_FOR_vec_widen_smult_lo_v16hi = 4357,
  CODE_FOR_vec_widen_umult_lo_v16hi = 4358,
  CODE_FOR_vec_widen_smult_lo_v8hi = 4359,
  CODE_FOR_vec_widen_umult_lo_v8hi = 4360,
  CODE_FOR_vec_widen_smult_lo_v8si = 4361,
  CODE_FOR_vec_widen_umult_lo_v8si = 4362,
  CODE_FOR_vec_widen_smult_lo_v4si = 4363,
  CODE_FOR_vec_widen_umult_lo_v4si = 4364,
  CODE_FOR_vec_widen_smult_even_v4si = 4365,
  CODE_FOR_vec_widen_smult_odd_v16si = 4366,
  CODE_FOR_vec_widen_umult_odd_v16si = 4367,
  CODE_FOR_vec_widen_smult_odd_v8si = 4368,
  CODE_FOR_vec_widen_umult_odd_v8si = 4369,
  CODE_FOR_vec_widen_smult_odd_v4si = 4370,
  CODE_FOR_vec_widen_umult_odd_v4si = 4371,
  CODE_FOR_sdot_prodv16hi = 4372,
  CODE_FOR_sdot_prodv8hi = 4373,
  CODE_FOR_sdot_prodv4si = 4374,
  CODE_FOR_vec_shl_v16qi = 4375,
  CODE_FOR_vec_shl_v8hi = 4376,
  CODE_FOR_vec_shl_v4si = 4377,
  CODE_FOR_vec_shl_v2di = 4378,
  CODE_FOR_vec_shr_v16qi = 4379,
  CODE_FOR_vec_shr_v8hi = 4380,
  CODE_FOR_vec_shr_v4si = 4381,
  CODE_FOR_vec_shr_v2di = 4382,
  CODE_FOR_smaxv32qi3 = 4383,
  CODE_FOR_sminv32qi3 = 4384,
  CODE_FOR_umaxv32qi3 = 4385,
  CODE_FOR_uminv32qi3 = 4386,
  CODE_FOR_smaxv16hi3 = 4387,
#define CODE_FOR_smaxv16hi3_round CODE_FOR_nothing
#define CODE_FOR_smaxv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv16hi3 = 4388,
#define CODE_FOR_sminv16hi3_round CODE_FOR_nothing
#define CODE_FOR_sminv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_sminv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv16hi3 = 4389,
#define CODE_FOR_umaxv16hi3_round CODE_FOR_nothing
#define CODE_FOR_umaxv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_umaxv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv16hi3 = 4390,
#define CODE_FOR_uminv16hi3_round CODE_FOR_nothing
#define CODE_FOR_uminv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_uminv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv8si3 = 4391,
#define CODE_FOR_smaxv8si3_round CODE_FOR_nothing
#define CODE_FOR_smaxv8si3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv8si3 = 4392,
#define CODE_FOR_sminv8si3_round CODE_FOR_nothing
#define CODE_FOR_sminv8si3_mask CODE_FOR_nothing
#define CODE_FOR_sminv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv8si3 = 4393,
#define CODE_FOR_umaxv8si3_round CODE_FOR_nothing
#define CODE_FOR_umaxv8si3_mask CODE_FOR_nothing
#define CODE_FOR_umaxv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv8si3 = 4394,
#define CODE_FOR_uminv8si3_round CODE_FOR_nothing
#define CODE_FOR_uminv8si3_mask CODE_FOR_nothing
#define CODE_FOR_uminv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv8di3 = 4395,
#define CODE_FOR_smaxv8di3_round CODE_FOR_nothing
  CODE_FOR_smaxv8di3_mask = 4396,
#define CODE_FOR_smaxv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv8di3 = 4397,
#define CODE_FOR_sminv8di3_round CODE_FOR_nothing
  CODE_FOR_sminv8di3_mask = 4398,
#define CODE_FOR_sminv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv8di3 = 4399,
#define CODE_FOR_umaxv8di3_round CODE_FOR_nothing
  CODE_FOR_umaxv8di3_mask = 4400,
#define CODE_FOR_umaxv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv8di3 = 4401,
#define CODE_FOR_uminv8di3_round CODE_FOR_nothing
  CODE_FOR_uminv8di3_mask = 4402,
#define CODE_FOR_uminv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv16si3 = 4403,
#define CODE_FOR_smaxv16si3_round CODE_FOR_nothing
  CODE_FOR_smaxv16si3_mask = 4404,
#define CODE_FOR_smaxv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv16si3 = 4405,
#define CODE_FOR_sminv16si3_round CODE_FOR_nothing
  CODE_FOR_sminv16si3_mask = 4406,
#define CODE_FOR_sminv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv16si3 = 4407,
#define CODE_FOR_umaxv16si3_round CODE_FOR_nothing
  CODE_FOR_umaxv16si3_mask = 4408,
#define CODE_FOR_umaxv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv16si3 = 4409,
#define CODE_FOR_uminv16si3_round CODE_FOR_nothing
  CODE_FOR_uminv16si3_mask = 4410,
#define CODE_FOR_uminv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv4di3 = 4411,
  CODE_FOR_sminv4di3 = 4412,
  CODE_FOR_umaxv4di3 = 4413,
  CODE_FOR_uminv4di3 = 4414,
  CODE_FOR_smaxv2di3 = 4415,
  CODE_FOR_sminv2di3 = 4416,
  CODE_FOR_umaxv2di3 = 4417,
  CODE_FOR_uminv2di3 = 4418,
  CODE_FOR_smaxv16qi3 = 4419,
  CODE_FOR_sminv16qi3 = 4420,
  CODE_FOR_smaxv8hi3 = 4421,
  CODE_FOR_sminv8hi3 = 4422,
  CODE_FOR_smaxv4si3 = 4423,
  CODE_FOR_sminv4si3 = 4424,
  CODE_FOR_umaxv16qi3 = 4425,
  CODE_FOR_uminv16qi3 = 4426,
  CODE_FOR_umaxv8hi3 = 4427,
  CODE_FOR_uminv8hi3 = 4428,
  CODE_FOR_umaxv4si3 = 4429,
  CODE_FOR_uminv4si3 = 4430,
  CODE_FOR_avx2_eqv32qi3 = 4431,
  CODE_FOR_avx2_eqv16hi3 = 4432,
  CODE_FOR_avx2_eqv8si3 = 4433,
  CODE_FOR_avx2_eqv4di3 = 4434,
  CODE_FOR_avx512f_eqv16si3 = 4435,
  CODE_FOR_avx512f_eqv16si3_mask = 4436,
  CODE_FOR_avx512f_eqv8di3 = 4437,
  CODE_FOR_avx512f_eqv8di3_mask = 4438,
  CODE_FOR_sse2_eqv16qi3 = 4439,
  CODE_FOR_sse2_eqv8hi3 = 4440,
  CODE_FOR_sse2_eqv4si3 = 4441,
  CODE_FOR_sse4_1_eqv2di3 = 4442,
  CODE_FOR_vcondv64qiv64qi = 4443,
  CODE_FOR_vcondv32hiv64qi = 4444,
  CODE_FOR_vcondv16siv64qi = 4445,
  CODE_FOR_vcondv8div64qi = 4446,
  CODE_FOR_vcondv16sfv64qi = 4447,
  CODE_FOR_vcondv8dfv64qi = 4448,
  CODE_FOR_vcondv64qiv32hi = 4449,
  CODE_FOR_vcondv32hiv32hi = 4450,
  CODE_FOR_vcondv16siv32hi = 4451,
  CODE_FOR_vcondv8div32hi = 4452,
  CODE_FOR_vcondv16sfv32hi = 4453,
  CODE_FOR_vcondv8dfv32hi = 4454,
  CODE_FOR_vcondv64qiv16si = 4455,
  CODE_FOR_vcondv32hiv16si = 4456,
  CODE_FOR_vcondv16siv16si = 4457,
  CODE_FOR_vcondv8div16si = 4458,
  CODE_FOR_vcondv16sfv16si = 4459,
  CODE_FOR_vcondv8dfv16si = 4460,
  CODE_FOR_vcondv64qiv8di = 4461,
  CODE_FOR_vcondv32hiv8di = 4462,
  CODE_FOR_vcondv16siv8di = 4463,
  CODE_FOR_vcondv8div8di = 4464,
  CODE_FOR_vcondv16sfv8di = 4465,
  CODE_FOR_vcondv8dfv8di = 4466,
  CODE_FOR_vcondv32qiv32qi = 4467,
  CODE_FOR_vcondv16hiv32qi = 4468,
  CODE_FOR_vcondv8siv32qi = 4469,
  CODE_FOR_vcondv4div32qi = 4470,
  CODE_FOR_vcondv8sfv32qi = 4471,
  CODE_FOR_vcondv4dfv32qi = 4472,
  CODE_FOR_vcondv32qiv16hi = 4473,
  CODE_FOR_vcondv16hiv16hi = 4474,
  CODE_FOR_vcondv8siv16hi = 4475,
  CODE_FOR_vcondv4div16hi = 4476,
  CODE_FOR_vcondv8sfv16hi = 4477,
  CODE_FOR_vcondv4dfv16hi = 4478,
  CODE_FOR_vcondv32qiv8si = 4479,
  CODE_FOR_vcondv16hiv8si = 4480,
  CODE_FOR_vcondv8siv8si = 4481,
  CODE_FOR_vcondv4div8si = 4482,
  CODE_FOR_vcondv8sfv8si = 4483,
  CODE_FOR_vcondv4dfv8si = 4484,
  CODE_FOR_vcondv32qiv4di = 4485,
  CODE_FOR_vcondv16hiv4di = 4486,
  CODE_FOR_vcondv8siv4di = 4487,
  CODE_FOR_vcondv4div4di = 4488,
  CODE_FOR_vcondv8sfv4di = 4489,
  CODE_FOR_vcondv4dfv4di = 4490,
  CODE_FOR_vcondv16qiv16qi = 4491,
  CODE_FOR_vcondv16qiv8hi = 4492,
  CODE_FOR_vcondv16qiv4si = 4493,
  CODE_FOR_vcondv8hiv16qi = 4494,
  CODE_FOR_vcondv8hiv8hi = 4495,
  CODE_FOR_vcondv8hiv4si = 4496,
  CODE_FOR_vcondv4siv16qi = 4497,
  CODE_FOR_vcondv4siv8hi = 4498,
  CODE_FOR_vcondv4siv4si = 4499,
  CODE_FOR_vcondv2div16qi = 4500,
  CODE_FOR_vcondv2div8hi = 4501,
  CODE_FOR_vcondv2div4si = 4502,
  CODE_FOR_vcondv4sfv16qi = 4503,
  CODE_FOR_vcondv4sfv8hi = 4504,
  CODE_FOR_vcondv4sfv4si = 4505,
  CODE_FOR_vcondv2dfv16qi = 4506,
  CODE_FOR_vcondv2dfv8hi = 4507,
  CODE_FOR_vcondv2dfv4si = 4508,
  CODE_FOR_vcondv2div2di = 4509,
  CODE_FOR_vcondv2dfv2di = 4510,
  CODE_FOR_vconduv64qiv64qi = 4511,
  CODE_FOR_vconduv32hiv64qi = 4512,
  CODE_FOR_vconduv16siv64qi = 4513,
  CODE_FOR_vconduv8div64qi = 4514,
  CODE_FOR_vconduv16sfv64qi = 4515,
  CODE_FOR_vconduv8dfv64qi = 4516,
  CODE_FOR_vconduv64qiv32hi = 4517,
  CODE_FOR_vconduv32hiv32hi = 4518,
  CODE_FOR_vconduv16siv32hi = 4519,
  CODE_FOR_vconduv8div32hi = 4520,
  CODE_FOR_vconduv16sfv32hi = 4521,
  CODE_FOR_vconduv8dfv32hi = 4522,
  CODE_FOR_vconduv64qiv16si = 4523,
  CODE_FOR_vconduv32hiv16si = 4524,
  CODE_FOR_vconduv16siv16si = 4525,
  CODE_FOR_vconduv8div16si = 4526,
  CODE_FOR_vconduv16sfv16si = 4527,
  CODE_FOR_vconduv8dfv16si = 4528,
  CODE_FOR_vconduv64qiv8di = 4529,
  CODE_FOR_vconduv32hiv8di = 4530,
  CODE_FOR_vconduv16siv8di = 4531,
  CODE_FOR_vconduv8div8di = 4532,
  CODE_FOR_vconduv16sfv8di = 4533,
  CODE_FOR_vconduv8dfv8di = 4534,
  CODE_FOR_vconduv32qiv32qi = 4535,
  CODE_FOR_vconduv16hiv32qi = 4536,
  CODE_FOR_vconduv8siv32qi = 4537,
  CODE_FOR_vconduv4div32qi = 4538,
  CODE_FOR_vconduv8sfv32qi = 4539,
  CODE_FOR_vconduv4dfv32qi = 4540,
  CODE_FOR_vconduv32qiv16hi = 4541,
  CODE_FOR_vconduv16hiv16hi = 4542,
  CODE_FOR_vconduv8siv16hi = 4543,
  CODE_FOR_vconduv4div16hi = 4544,
  CODE_FOR_vconduv8sfv16hi = 4545,
  CODE_FOR_vconduv4dfv16hi = 4546,
  CODE_FOR_vconduv32qiv8si = 4547,
  CODE_FOR_vconduv16hiv8si = 4548,
  CODE_FOR_vconduv8siv8si = 4549,
  CODE_FOR_vconduv4div8si = 4550,
  CODE_FOR_vconduv8sfv8si = 4551,
  CODE_FOR_vconduv4dfv8si = 4552,
  CODE_FOR_vconduv32qiv4di = 4553,
  CODE_FOR_vconduv16hiv4di = 4554,
  CODE_FOR_vconduv8siv4di = 4555,
  CODE_FOR_vconduv4div4di = 4556,
  CODE_FOR_vconduv8sfv4di = 4557,
  CODE_FOR_vconduv4dfv4di = 4558,
  CODE_FOR_vconduv16qiv16qi = 4559,
  CODE_FOR_vconduv16qiv8hi = 4560,
  CODE_FOR_vconduv16qiv4si = 4561,
  CODE_FOR_vconduv8hiv16qi = 4562,
  CODE_FOR_vconduv8hiv8hi = 4563,
  CODE_FOR_vconduv8hiv4si = 4564,
  CODE_FOR_vconduv4siv16qi = 4565,
  CODE_FOR_vconduv4siv8hi = 4566,
  CODE_FOR_vconduv4siv4si = 4567,
  CODE_FOR_vconduv2div16qi = 4568,
  CODE_FOR_vconduv2div8hi = 4569,
  CODE_FOR_vconduv2div4si = 4570,
  CODE_FOR_vconduv4sfv16qi = 4571,
  CODE_FOR_vconduv4sfv8hi = 4572,
  CODE_FOR_vconduv4sfv4si = 4573,
  CODE_FOR_vconduv2dfv16qi = 4574,
  CODE_FOR_vconduv2dfv8hi = 4575,
  CODE_FOR_vconduv2dfv4si = 4576,
  CODE_FOR_vconduv2div2di = 4577,
  CODE_FOR_vconduv2dfv2di = 4578,
  CODE_FOR_vec_permv16qi = 4579,
  CODE_FOR_vec_permv8hi = 4580,
  CODE_FOR_vec_permv4si = 4581,
  CODE_FOR_vec_permv2di = 4582,
  CODE_FOR_vec_permv4sf = 4583,
  CODE_FOR_vec_permv2df = 4584,
  CODE_FOR_vec_permv32qi = 4585,
  CODE_FOR_vec_permv16hi = 4586,
  CODE_FOR_vec_permv8si = 4587,
  CODE_FOR_vec_permv4di = 4588,
  CODE_FOR_vec_permv8sf = 4589,
  CODE_FOR_vec_permv4df = 4590,
  CODE_FOR_vec_permv16sf = 4591,
  CODE_FOR_vec_permv8df = 4592,
  CODE_FOR_vec_permv16si = 4593,
  CODE_FOR_vec_permv8di = 4594,
  CODE_FOR_vec_perm_constv4sf = 4595,
  CODE_FOR_vec_perm_constv4si = 4596,
  CODE_FOR_vec_perm_constv2df = 4597,
  CODE_FOR_vec_perm_constv2di = 4598,
  CODE_FOR_vec_perm_constv16qi = 4599,
  CODE_FOR_vec_perm_constv8hi = 4600,
  CODE_FOR_vec_perm_constv8sf = 4601,
  CODE_FOR_vec_perm_constv4df = 4602,
  CODE_FOR_vec_perm_constv8si = 4603,
  CODE_FOR_vec_perm_constv4di = 4604,
  CODE_FOR_vec_perm_constv32qi = 4605,
  CODE_FOR_vec_perm_constv16hi = 4606,
  CODE_FOR_vec_perm_constv16si = 4607,
  CODE_FOR_vec_perm_constv8di = 4608,
  CODE_FOR_vec_perm_constv16sf = 4609,
  CODE_FOR_vec_perm_constv8df = 4610,
  CODE_FOR_one_cmplv16si2 = 4611,
  CODE_FOR_one_cmplv8di2 = 4612,
  CODE_FOR_one_cmplv32qi2 = 4613,
  CODE_FOR_one_cmplv16qi2 = 4614,
  CODE_FOR_one_cmplv16hi2 = 4615,
  CODE_FOR_one_cmplv8hi2 = 4616,
  CODE_FOR_one_cmplv8si2 = 4617,
  CODE_FOR_one_cmplv4si2 = 4618,
  CODE_FOR_one_cmplv4di2 = 4619,
  CODE_FOR_one_cmplv2di2 = 4620,
  CODE_FOR_avx2_andnotv32qi3 = 4621,
  CODE_FOR_sse2_andnotv16qi3 = 4622,
#define CODE_FOR_sse2_andnotv16qi3_mask CODE_FOR_nothing
  CODE_FOR_avx2_andnotv16hi3 = 4623,
#define CODE_FOR_avx2_andnotv16hi3_mask CODE_FOR_nothing
  CODE_FOR_sse2_andnotv8hi3 = 4624,
#define CODE_FOR_sse2_andnotv8hi3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_andnotv16si3 = 4625,
  CODE_FOR_avx512f_andnotv16si3_mask = 4626,
  CODE_FOR_avx2_andnotv8si3 = 4627,
#define CODE_FOR_avx2_andnotv8si3_mask CODE_FOR_nothing
  CODE_FOR_sse2_andnotv4si3 = 4628,
#define CODE_FOR_sse2_andnotv4si3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_andnotv8di3 = 4629,
  CODE_FOR_avx512f_andnotv8di3_mask = 4630,
  CODE_FOR_avx2_andnotv4di3 = 4631,
#define CODE_FOR_avx2_andnotv4di3_mask CODE_FOR_nothing
  CODE_FOR_sse2_andnotv2di3 = 4632,
#define CODE_FOR_sse2_andnotv2di3_mask CODE_FOR_nothing
  CODE_FOR_andv16si3 = 4633,
  CODE_FOR_iorv16si3 = 4634,
  CODE_FOR_xorv16si3 = 4635,
  CODE_FOR_andv8di3 = 4636,
  CODE_FOR_iorv8di3 = 4637,
  CODE_FOR_xorv8di3 = 4638,
  CODE_FOR_andv32qi3 = 4639,
  CODE_FOR_iorv32qi3 = 4640,
  CODE_FOR_xorv32qi3 = 4641,
  CODE_FOR_andv16qi3 = 4642,
  CODE_FOR_iorv16qi3 = 4643,
  CODE_FOR_xorv16qi3 = 4644,
  CODE_FOR_andv16hi3 = 4645,
  CODE_FOR_iorv16hi3 = 4646,
  CODE_FOR_xorv16hi3 = 4647,
  CODE_FOR_andv8hi3 = 4648,
  CODE_FOR_iorv8hi3 = 4649,
  CODE_FOR_xorv8hi3 = 4650,
  CODE_FOR_andv8si3 = 4651,
  CODE_FOR_iorv8si3 = 4652,
  CODE_FOR_xorv8si3 = 4653,
  CODE_FOR_andv4si3 = 4654,
  CODE_FOR_iorv4si3 = 4655,
  CODE_FOR_xorv4si3 = 4656,
  CODE_FOR_andv4di3 = 4657,
  CODE_FOR_iorv4di3 = 4658,
  CODE_FOR_xorv4di3 = 4659,
  CODE_FOR_andv2di3 = 4660,
  CODE_FOR_iorv2di3 = 4661,
  CODE_FOR_xorv2di3 = 4662,
  CODE_FOR_vec_pack_trunc_v16hi = 4663,
  CODE_FOR_vec_pack_trunc_v8hi = 4664,
  CODE_FOR_vec_pack_trunc_v8si = 4665,
  CODE_FOR_vec_pack_trunc_v4si = 4666,
  CODE_FOR_vec_pack_trunc_v8di = 4667,
  CODE_FOR_vec_pack_trunc_v4di = 4668,
  CODE_FOR_vec_pack_trunc_v2di = 4669,
  CODE_FOR_vec_interleave_highv32qi = 4670,
  CODE_FOR_vec_interleave_highv16hi = 4671,
  CODE_FOR_vec_interleave_highv8si = 4672,
  CODE_FOR_vec_interleave_highv4di = 4673,
  CODE_FOR_vec_interleave_lowv32qi = 4674,
  CODE_FOR_vec_interleave_lowv16hi = 4675,
  CODE_FOR_vec_interleave_lowv8si = 4676,
  CODE_FOR_vec_interleave_lowv4di = 4677,
  CODE_FOR_avx512f_vinsertf32x4_mask = 4678,
  CODE_FOR_avx512f_vinserti32x4_mask = 4679,
  CODE_FOR_avx512f_vinsertf64x4_mask = 4680,
  CODE_FOR_avx512f_vinserti64x4_mask = 4681,
  CODE_FOR_avx512f_shuf_f64x2_mask = 4682,
  CODE_FOR_avx512f_shuf_i64x2_mask = 4683,
  CODE_FOR_avx512f_shuf_f32x4_mask = 4684,
  CODE_FOR_avx512f_shuf_i32x4_mask = 4685,
  CODE_FOR_avx512f_pshufdv3_mask = 4686,
  CODE_FOR_avx2_pshufdv3 = 4687,
  CODE_FOR_sse2_pshufd = 4688,
  CODE_FOR_avx2_pshuflwv3 = 4689,
  CODE_FOR_sse2_pshuflw = 4690,
  CODE_FOR_avx2_pshufhwv3 = 4691,
  CODE_FOR_sse2_pshufhw = 4692,
  CODE_FOR_sse2_loadd = 4693,
  CODE_FOR_vec_unpacks_lo_v32qi = 4700,
  CODE_FOR_vec_unpacks_lo_v16qi = 4701,
  CODE_FOR_vec_unpacks_lo_v32hi = 4702,
  CODE_FOR_vec_unpacks_lo_v16hi = 4703,
  CODE_FOR_vec_unpacks_lo_v8hi = 4704,
  CODE_FOR_vec_unpacks_lo_v16si = 4705,
  CODE_FOR_vec_unpacks_lo_v8si = 4706,
  CODE_FOR_vec_unpacks_lo_v4si = 4707,
  CODE_FOR_vec_unpacks_hi_v32qi = 4708,
  CODE_FOR_vec_unpacks_hi_v16qi = 4709,
  CODE_FOR_vec_unpacks_hi_v32hi = 4710,
  CODE_FOR_vec_unpacks_hi_v16hi = 4711,
  CODE_FOR_vec_unpacks_hi_v8hi = 4712,
  CODE_FOR_vec_unpacks_hi_v16si = 4713,
  CODE_FOR_vec_unpacks_hi_v8si = 4714,
  CODE_FOR_vec_unpacks_hi_v4si = 4715,
  CODE_FOR_vec_unpacku_lo_v32qi = 4716,
  CODE_FOR_vec_unpacku_lo_v16qi = 4717,
  CODE_FOR_vec_unpacku_lo_v32hi = 4718,
  CODE_FOR_vec_unpacku_lo_v16hi = 4719,
  CODE_FOR_vec_unpacku_lo_v8hi = 4720,
  CODE_FOR_vec_unpacku_lo_v16si = 4721,
  CODE_FOR_vec_unpacku_lo_v8si = 4722,
  CODE_FOR_vec_unpacku_lo_v4si = 4723,
  CODE_FOR_vec_unpacku_hi_v32qi = 4724,
  CODE_FOR_vec_unpacku_hi_v16qi = 4725,
  CODE_FOR_vec_unpacku_hi_v32hi = 4726,
  CODE_FOR_vec_unpacku_hi_v16hi = 4727,
  CODE_FOR_vec_unpacku_hi_v8hi = 4728,
  CODE_FOR_vec_unpacku_hi_v16si = 4729,
  CODE_FOR_vec_unpacku_hi_v8si = 4730,
  CODE_FOR_vec_unpacku_hi_v4si = 4731,
  CODE_FOR_avx2_uavgv32qi3 = 4732,
  CODE_FOR_sse2_uavgv16qi3 = 4733,
  CODE_FOR_avx2_uavgv16hi3 = 4734,
  CODE_FOR_sse2_uavgv8hi3 = 4735,
  CODE_FOR_sse2_maskmovdqu = 4736,
  CODE_FOR_ssse3_pmulhrswv4hi3 = 4737,
  CODE_FOR_ssse3_pmulhrswv8hi3 = 4738,
  CODE_FOR_avx2_pmulhrswv16hi3 = 4739,
  CODE_FOR_absv32qi2 = 4740,
  CODE_FOR_absv16qi2 = 4741,
  CODE_FOR_absv16hi2 = 4742,
  CODE_FOR_absv8hi2 = 4743,
  CODE_FOR_absv16si2 = 4744,
  CODE_FOR_absv8si2 = 4745,
  CODE_FOR_absv4si2 = 4746,
  CODE_FOR_absv8di2 = 4747,
  CODE_FOR_avx2_pblendw = 4748,
  CODE_FOR_avx_roundps_sfix256 = 4749,
  CODE_FOR_sse4_1_roundps_sfix = 4750,
  CODE_FOR_avx512f_roundpd512 = 4751,
  CODE_FOR_avx512f_roundpd_vec_pack_sfix512 = 4752,
  CODE_FOR_avx_roundpd_vec_pack_sfix256 = 4753,
  CODE_FOR_sse4_1_roundpd_vec_pack_sfix = 4754,
  CODE_FOR_roundv16sf2 = 4755,
  CODE_FOR_roundv8sf2 = 4756,
  CODE_FOR_roundv4sf2 = 4757,
  CODE_FOR_roundv8df2 = 4758,
  CODE_FOR_roundv4df2 = 4759,
  CODE_FOR_roundv2df2 = 4760,
  CODE_FOR_roundv8sf2_sfix = 4761,
  CODE_FOR_roundv4sf2_sfix = 4762,
  CODE_FOR_roundv8df2_vec_pack_sfix = 4763,
  CODE_FOR_roundv4df2_vec_pack_sfix = 4764,
  CODE_FOR_roundv2df2_vec_pack_sfix = 4765,
  CODE_FOR_avx512pf_gatherpfv16sisf = 4770,
  CODE_FOR_avx512pf_gatherpfv8disf = 4771,
  CODE_FOR_avx512pf_gatherpfv8sidf = 4772,
  CODE_FOR_avx512pf_gatherpfv8didf = 4773,
  CODE_FOR_avx512pf_scatterpfv16sisf = 4774,
  CODE_FOR_avx512pf_scatterpfv8disf = 4775,
  CODE_FOR_avx512pf_scatterpfv8sidf = 4776,
  CODE_FOR_avx512pf_scatterpfv8didf = 4777,
  CODE_FOR_rotlv16qi3 = 4778,
  CODE_FOR_rotlv8hi3 = 4779,
  CODE_FOR_rotlv4si3 = 4780,
  CODE_FOR_rotlv2di3 = 4781,
  CODE_FOR_rotrv16qi3 = 4782,
  CODE_FOR_rotrv8hi3 = 4783,
  CODE_FOR_rotrv4si3 = 4784,
  CODE_FOR_rotrv2di3 = 4785,
  CODE_FOR_vrotrv16qi3 = 4786,
  CODE_FOR_vrotrv8hi3 = 4787,
  CODE_FOR_vrotrv4si3 = 4788,
  CODE_FOR_vrotrv2di3 = 4789,
  CODE_FOR_vrotlv16qi3 = 4790,
  CODE_FOR_vrotlv8hi3 = 4791,
  CODE_FOR_vrotlv4si3 = 4792,
  CODE_FOR_vrotlv2di3 = 4793,
  CODE_FOR_vlshrv16qi3 = 4794,
  CODE_FOR_vlshrv8hi3 = 4795,
  CODE_FOR_vlshrv4si3 = 4796,
  CODE_FOR_vlshrv2di3 = 4797,
  CODE_FOR_vlshrv16si3 = 4798,
  CODE_FOR_vlshrv8di3 = 4799,
  CODE_FOR_vlshrv8si3 = 4800,
  CODE_FOR_vlshrv4di3 = 4801,
  CODE_FOR_vashrv16qi3 = 4802,
  CODE_FOR_vashrv8hi3 = 4803,
  CODE_FOR_vashrv2di3 = 4804,
  CODE_FOR_vashrv4si3 = 4805,
  CODE_FOR_vashrv16si3 = 4806,
  CODE_FOR_vashrv8si3 = 4807,
  CODE_FOR_vashlv16qi3 = 4808,
  CODE_FOR_vashlv8hi3 = 4809,
  CODE_FOR_vashlv4si3 = 4810,
  CODE_FOR_vashlv2di3 = 4811,
  CODE_FOR_vashlv16si3 = 4812,
  CODE_FOR_vashlv8di3 = 4813,
  CODE_FOR_vashlv8si3 = 4814,
  CODE_FOR_vashlv4di3 = 4815,
  CODE_FOR_ashlv32qi3 = 4816,
  CODE_FOR_lshrv32qi3 = 4817,
  CODE_FOR_ashrv32qi3 = 4818,
  CODE_FOR_ashlv16qi3 = 4819,
  CODE_FOR_lshrv16qi3 = 4820,
  CODE_FOR_ashrv16qi3 = 4821,
  CODE_FOR_ashrv2di3 = 4822,
  CODE_FOR_xop_vmfrczv4sf2 = 4823,
  CODE_FOR_xop_vmfrczv2df2 = 4824,
  CODE_FOR_avx_vzeroall = 4825,
  CODE_FOR_avx2_permv4di = 4826,
  CODE_FOR_avx2_permv4df = 4827,
  CODE_FOR_avx512f_permv8di = 4828,
  CODE_FOR_avx512f_permv8df = 4829,
  CODE_FOR_avx512f_permv8df_mask = 4830,
  CODE_FOR_avx512f_permv8di_mask = 4831,
  CODE_FOR_avx512f_vpermilv8df = 4838,
  CODE_FOR_avx512f_vpermilv8df_mask = 4839,
  CODE_FOR_avx_vpermilv4df = 4840,
#define CODE_FOR_avx_vpermilv4df_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilv2df = 4841,
#define CODE_FOR_avx_vpermilv2df_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermilv16sf = 4842,
  CODE_FOR_avx512f_vpermilv16sf_mask = 4843,
  CODE_FOR_avx_vpermilv8sf = 4844,
#define CODE_FOR_avx_vpermilv8sf_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilv4sf = 4845,
#define CODE_FOR_avx_vpermilv4sf_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermi2varv16si3_maskz = 4846,
  CODE_FOR_avx512f_vpermi2varv16sf3_maskz = 4847,
  CODE_FOR_avx512f_vpermi2varv8di3_maskz = 4848,
  CODE_FOR_avx512f_vpermi2varv8df3_maskz = 4849,
  CODE_FOR_avx512f_vpermt2varv16si3_maskz = 4850,
  CODE_FOR_avx512f_vpermt2varv16sf3_maskz = 4851,
  CODE_FOR_avx512f_vpermt2varv8di3_maskz = 4852,
  CODE_FOR_avx512f_vpermt2varv8df3_maskz = 4853,
  CODE_FOR_avx_vperm2f128v8si3 = 4854,
  CODE_FOR_avx_vperm2f128v8sf3 = 4855,
  CODE_FOR_avx_vperm2f128v4df3 = 4856,
  CODE_FOR_avx_vinsertf128v32qi = 4857,
  CODE_FOR_avx_vinsertf128v16hi = 4858,
  CODE_FOR_avx_vinsertf128v8si = 4859,
  CODE_FOR_avx_vinsertf128v4di = 4860,
  CODE_FOR_avx_vinsertf128v8sf = 4861,
  CODE_FOR_avx_vinsertf128v4df = 4862,
  CODE_FOR_maskloadv4sf = 4863,
  CODE_FOR_maskloadv2df = 4864,
  CODE_FOR_maskloadv8sf = 4865,
  CODE_FOR_maskloadv4df = 4866,
  CODE_FOR_maskloadv4si = 4867,
  CODE_FOR_maskloadv2di = 4868,
  CODE_FOR_maskloadv8si = 4869,
  CODE_FOR_maskloadv4di = 4870,
  CODE_FOR_maskstorev4sf = 4871,
  CODE_FOR_maskstorev2df = 4872,
  CODE_FOR_maskstorev8sf = 4873,
  CODE_FOR_maskstorev4df = 4874,
  CODE_FOR_maskstorev4si = 4875,
  CODE_FOR_maskstorev2di = 4876,
  CODE_FOR_maskstorev8si = 4877,
  CODE_FOR_maskstorev4di = 4878,
  CODE_FOR_vec_initv32qi = 4882,
  CODE_FOR_vec_initv16hi = 4883,
  CODE_FOR_vec_initv8si = 4884,
  CODE_FOR_vec_initv4di = 4885,
  CODE_FOR_vec_initv8sf = 4886,
  CODE_FOR_vec_initv4df = 4887,
  CODE_FOR_vec_initv16si = 4888,
  CODE_FOR_vec_initv16sf = 4889,
  CODE_FOR_vec_initv8di = 4890,
  CODE_FOR_vec_initv8df = 4891,
  CODE_FOR_avx2_extracti128 = 4892,
  CODE_FOR_avx2_inserti128 = 4893,
  CODE_FOR_vcvtps2ph = 4894,
  CODE_FOR_avx2_gathersiv2di = 4895,
  CODE_FOR_avx2_gathersiv2df = 4896,
  CODE_FOR_avx2_gathersiv4di = 4897,
  CODE_FOR_avx2_gathersiv4df = 4898,
  CODE_FOR_avx2_gathersiv4si = 4899,
  CODE_FOR_avx2_gathersiv4sf = 4900,
  CODE_FOR_avx2_gathersiv8si = 4901,
  CODE_FOR_avx2_gathersiv8sf = 4902,
  CODE_FOR_avx2_gatherdiv2di = 4903,
  CODE_FOR_avx2_gatherdiv2df = 4904,
  CODE_FOR_avx2_gatherdiv4di = 4905,
  CODE_FOR_avx2_gatherdiv4df = 4906,
  CODE_FOR_avx2_gatherdiv4si = 4907,
  CODE_FOR_avx2_gatherdiv4sf = 4908,
  CODE_FOR_avx2_gatherdiv8si = 4909,
  CODE_FOR_avx2_gatherdiv8sf = 4910,
  CODE_FOR_avx512f_gathersiv16si = 4911,
  CODE_FOR_avx512f_gathersiv16sf = 4912,
  CODE_FOR_avx512f_gathersiv8di = 4913,
  CODE_FOR_avx512f_gathersiv8df = 4914,
  CODE_FOR_avx512f_gatherdiv16si = 4915,
  CODE_FOR_avx512f_gatherdiv16sf = 4916,
  CODE_FOR_avx512f_gatherdiv8di = 4917,
  CODE_FOR_avx512f_gatherdiv8df = 4918,
  CODE_FOR_avx512f_scattersiv16si = 4919,
  CODE_FOR_avx512f_scattersiv16sf = 4920,
  CODE_FOR_avx512f_scattersiv8di = 4921,
  CODE_FOR_avx512f_scattersiv8df = 4922,
  CODE_FOR_avx512f_scatterdiv16si = 4923,
  CODE_FOR_avx512f_scatterdiv16sf = 4924,
  CODE_FOR_avx512f_scatterdiv8di = 4925,
  CODE_FOR_avx512f_scatterdiv8df = 4926,
  CODE_FOR_avx512f_expandv16si_maskz = 4927,
  CODE_FOR_avx512f_expandv16sf_maskz = 4928,
  CODE_FOR_avx512f_expandv8di_maskz = 4929,
  CODE_FOR_avx512f_expandv8df_maskz = 4930,
  CODE_FOR_sse2_lfence = 4931,
  CODE_FOR_sse_sfence = 4932,
  CODE_FOR_sse2_mfence = 4933,
  CODE_FOR_mem_thread_fence = 4934,
  CODE_FOR_atomic_loadqi = 4935,
  CODE_FOR_atomic_loadhi = 4936,
  CODE_FOR_atomic_loadsi = 4937,
  CODE_FOR_atomic_loaddi = 4938,
  CODE_FOR_atomic_storeqi = 4940,
  CODE_FOR_atomic_storehi = 4941,
  CODE_FOR_atomic_storesi = 4942,
  CODE_FOR_atomic_storedi = 4943,
  CODE_FOR_atomic_compare_and_swapqi = 4945,
  CODE_FOR_atomic_compare_and_swaphi = 4946,
  CODE_FOR_atomic_compare_and_swapsi = 4947,
  CODE_FOR_atomic_compare_and_swapdi = 4948,
#define CODE_FOR_atomic_compare_and_swapti CODE_FOR_nothing
  LAST_INSN_CODE
};

#endif /* GCC_INSN_CODES_H */
