# Define SciTE settings for vhdl files.

# VHDL files
file.patterns.vhdl=*.vhd;*.vhdl
filter.vhdl=VHDL (vhd vhdl)|$(file.patterns.vhdl)|

lexer.$(file.patterns.vhdl)=vhdl

word.chars.vhdl=$(chars.alpha)$(chars.numeric)_
word.characters.$(file.patterns.vhdl)=$(word.chars.vhdl)

#calltip.vhdl.word.characters=$(chars.alpha)$(chars.numeric)_

comment.block.vhdl=--
#comment.block.at.line.start.vhdl=1
#comment.stream.start.vhdl=/*
#comment.stream.end.vhdl=*/
#comment.box.start.vhdl=/*
#comment.box.middle.vhdl= *
#comment.box.end.vhdl= */

#~ fold.at.Begin=1
#~ fold.at.Parenthese=1

#statement.lookback.$(file.patterns.vhdl)=20
#block.start.$(file.patterns.vhdl)=5 begin
#block.end.$(file.patterns.vhdl)=5 end
#statement.indent.$(file.patterns.vhdl)=5 always case casex casez else for if while \
#module function task

indent.maintain.$(file.patterns.vhdl)=1;


keywords.$(file.patterns.vhdl)=access after alias all architecture array assert attribute begin block \
body buffer bus case component configuration constant disconnect downto else elsif end entity exit file \
for function generate generic group guarded if impure in inertial inout is label library linkage literal \
loop map new next null of on open others out package port postponed procedure process pure range record \
register reject report return select severity shared signal subtype then to transport type unaffected \
units until use variable wait when while with

keywords2.$(file.patterns.vhdl)=                                                                            \
 abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor

keywords3.$(file.patterns.vhdl)=                                                                            \
 left right low high ascending image value pos val succ pred leftof rightof base range reverse_range        \
 length delayed stable quiet transaction event active last_event last_active last_value driving             \
 driving_value simple_name path_name instance_name

keywords4.$(file.patterns.vhdl)=                                                                            \
 now readline read writeline write endfile resolved to_bit to_bitvector to_stdulogic to_stdlogicvector      \
 to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x shift_left shift_right rotate_left \
 rotate_right resize to_integer to_unsigned to_signed std_match to_01

keywords5.$(file.patterns.vhdl)=                                                                            \
 std ieee work standard textio std_logic_1164 std_logic_arith std_logic_misc std_logic_signed               \
 std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives        \
 vital_timing

keywords6.$(file.patterns.vhdl)=                                                                            \
 boolean bit character severity_level integer real time delay_length natural positive string bit_vector     \
 file_open_kind file_open_status line text side width std_ulogic std_ulogic_vector std_logic                \
 std_logic_vector X01 X01Z UX01 UX01Z unsigned signed

# vhdl styles

# Default
style.vhdl.32=$(font.base)
# White space
style.vhdl.0=fore:#800080
# Comment
style.vhdl.1=$(colour.code.comment.line),$(font.code.comment.line)
# Bang comment
style.vhdl.2=fore:#3F7F3F,$(font.code.comment.line)
# Number
style.vhdl.3=$(colour.number)
# Double quoted string
style.vhdl.4=$(colour.string)
# Operators
#style.vhdl.5=$(colour.operator)
# Identifiers
style.vhdl.6=
# End of line where string is not closed
style.vhdl.7=fore:#000000,$(font.string.literal),back:#E0C0E0,eolfilled
# Keyword
style.vhdl.8=$(colour.keyword)
# Std operator
style.vhdl.9=fore:#007F7F
# Attribute
style.vhdl.10=fore:#804020
# Std Function
style.vhdl.11=fore:#808020
# Std Package
style.vhdl.12=fore:#208020
# Std Type
style.vhdl.13=fore:#208080
# User defined identifiers and tasks
style.vhdl.14=fore:#804020,$(font.code.comment.doc)
# Braces are only matched in operator style
braces.vhdl.style=5
